V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

15.4.4. 10G PCS Parameters for Arria V GZ Native PHY

This section shows the complete datapath and clocking for the 10G PCS and defines parameters available in the GUI to enable or disable the individual blocks in the 10G PCS.

Figure 80. The 10G PCS datapath
Table 272.  General and Datapath Parameters
Parameter Range Description
10G PCS protocol mode

basic

interlaken

sfi5

teng_baser

teng_sdi

Specifies the protocol that you intend to implement with the Native PHY. The protocol mode selected guides the MegaWizard in identifying legal settings for the 10G PCS datapath. Use the following guidelines to select a protocol mode:
  • basic : Select this mode for when none of the other options are appropriate. You should also select this mode to enable diagnostics, such as loopback.
  • interlaken: Select this mode if you intend to implement Interlaken.
  • sfi5 : Select this mode if you intend to implement the SERDES Framer Interface Level 5 protocol.
  • teng_baser : select this mode if you intend to implement the 10GBASE‑R protocol.
  • teng_sdi : 10G SDI
10G PCS/PMA interface width 32, 40, 64 Specifies the width of the datapath that connects the FPGA fabric to the PMA.
FPGA fabric/10G PCS interface width

32

40

50

64

66

67

Specifies the FPGA fabric to TX PCS interface width .

The 66-bit FPGA fabric/PCS interface width is achieved using 64-bits from the TX and RX parallel data and the lower 2-bits from the control bus.

The 67-bit FPGA fabric/PCS interface width is achieved using the 64-bits from the TX and RX parallel data and the lower 3-bits from the control bus.

10G TX FIFO

The TX FIFO is the interface between TX data from the FPGA fabric and the PCS. This FIFO is an asynchronous 73-bit wide, 32-deep memory buffer It also provides full, empty, partially full, and empty flags based on programmable thresholds. The following table describes the 10G TX FIFO parameters.

Table 273.  10G TX FIFO Parameters
Parameter Range Description
TX FIFO Mode

Interlaken

phase_comp

register

Specifies one of the following 3 modes:
  • interlaken : The TX FIFO acts as an elastic buffer. The FIFO write clock frequency (coreclk) can exceed that of the effective read clock, tx_clkout. You can control writes to the FIFO with tx_data_valid. By monitoring the FIFO flags, you can avoid the FIFO full and empty conditions. The Interlaken frame generator controls reads.
  • phase_comp : The TX FIFO compensates for the clock phase difference between the coreclkin and tx_clkout which is an internal PCS clock.
  • register : The TX FIFO is bypassed. tx_data and tx_data_valid are registered at the FIFO output. You must control tx_data_valid precisely based on gearbox ratio to avoid gearbox underflow or overflow conditions.
TX FIFO full threshold 0-31 Specifies the full threshold for the 10G PCS TX FIFO. The active high TX FIFO full flag is synchronous to coreclk. The default value is 31.
TX FIFO empty threshold 0-31 Specifies the empty threshold for the 10G PCS TX FIFO. The active high TX FIFO empty flag is synchronous to coreclk. The default value is 0.
TX FIFO partially full threshold 0-31 Specifies the partially full threshold for the 10G PCS TX FIFO. The active high TX FIFO partially full flag is synchronous to coreclk. The default value is 23.
TX FIFO partially empty threshold 0-31 Specifies the partially empty threshold for the 10G PCS TX FIFO. The active high TX FIFO partially empty flag is synchronous to coreclk.
Enable tx_10g_fifo_full port On/Off When you turn this option On , the 10G PCS includes the active high tx_10g_fifo_full port. tx_10g_fifo_full is synchronous to coreclk.
Enable tx_10g_fifo_pfull port On/Off When you turn this option On , the 10G PCS includes the active high tx_10g_fifo_pfull port. tx_10g_fifo_pfull is synchronous to coreclk.
Enable tx_10g_fifo_empty port On/Off When you turn this option On, the 10G PCS includes the active high tx_10g_fifo_empty port. tx_10g_fifo_empty is pulse‑stretched. It is asynchronous to coreclk and synchronous to tx_clkout which is the read clock.
Enable tx_10g_fifo_pempty port On/Off When you turn this option On, the 10G PCS includes the tx_10g_fifo_pempty port.
Enable tx_10g_fifo_del port (10GBASE‑R) On/Off When you turn this option On, the 10G PCS includes the active high tx_10g_fifo_del port. This signal is asserted when a word is deleted from the TX FIFO. This signal is only used for the 10GBASE‑R protocol.
Enable tx_10g_fifo_insert port (10GBASE‑R) On/Off When you turn this option On, the 10G PCS includes the active high tx_10g_fifo_insert port. This signal is asserted when a word is inserted into the TX FIFO. This signal is only used for the 10GBASE‑R protocol.

10G RX FIFO

The RX FIFO is the interface between RX data from the FPGA fabric and the PCS. This FIFO is an asynchronous 73-bit wide, 32-deep memory buffer It also provides full, empty, partially full, and empty flags based on programmable thresholds. The following table describes the 10G RX FIFO parameters.

Table 274.  10G RX FIFO Parameters
Parameter Range Description
RX FIFO Mode

Interlaken

clk_comp

phase_comp

register

Specifies one of the following 3 modes:
  • interlaken : Select this mode for the Interlaken protocol. To implement the deskew process. In this mode the FIFO acts as an elastic buffer. The FIFO write clock can exceed the read clock. Your implementation must control the FIFO write (tx_datavalid) by monitoring the FIFO flags. The read enable is controlled by the Interlaken Frame Generator.
  • clk_comp : This mode compensates for the clock difference between the PLD clock (coreclkin) and rxclkout. After block lock is achieved, idle ordered set insertions and deletions compensate for the clock difference between RX PMA clock and PLD clock up to ± 100 ppm. Use this mode for 10GBASE‑R.
  • phase_comp : This mode compensates for the clock phase difference between the PLD clock (coreclkin) and rxclkout.
  • register : The TX FIFO is bypassed. rx_data and rx_data_valid are registered at the FIFO output.
RX FIFO full threshold 0-31 Specifies the full threshold for the 10G PCS RX FIFO. The default value is 31.
RX FIFO empty threshold 0-31 Specifies the empty threshold for the 10G PCS RX FIFO. The default value is 0.
RX FIFO partially full threshold 0-31 Specifies the partially full threshold for the 10G PCS RX FIFO. The default value is 23.
RX FIFO partially empty threshold 0-31 Specifies the partially empty threshold for the 10G PCS RX FIFO.
Enable RX FIFO deskew (interlaken) On/ Off When you turn this option On, the RX FIFO also performs deskew. This option is only available for the Interlaken protocol.
Enable RX FIFO alignment word deletion (interlaken) On/Off When you turn this option On, all alignment words (sync words), including the first sync word, are removed after frame synchronization is achieved. If you enable this option, you must also enable control word deletion.
Enable RX FIFO control word deletion (interlaken) On/Off When you turn this option On , the rx_control_del parameter enables or disables writing the Interlaken control word to RX FIFO. When disabled, a value of 0 for rx_control_del writes all control words to RX FIFO. When enabled, a value of 1 deletes all control words and only writes the data to the RX FIFO.
Enable rx_10g_fifo_data_valid port On/Off When you turn this option On, the 10G PCS includes the rx_data_valid signal which Indicates when rx_data is valid. This option is available when you select the following parameters:
  • 10G PCS protocol mode is Interlaken
  • 10G PCS protocol mode is Basic and RX FIFO mode is phase_comp
  • 10G PCS protocol mode is Basic and RX FIFO mode is register
Enable rx_10g_fifo_full port On/Off When you turn this option On, the 10G PCS includes the active high rx_10g_fifo_full port. rx_10g_fifo_full is synchronous to rx_clkout.
Enable rx_10g_fifo_pfull port On/Off When you turn this option On, the 10G PCS includes the active high rx_10g_fifo_pfull port. rx_10g_fifo_pfull is synchronous to rx_clkout.
Enable rx_10g_fifo_empty port On/Off When you turn this option On, the 10G PCS includes the active high rx_10g_fifo_empty port.
Enable rx_10g_fifo_pempty port On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_pempty port.
Enable rx_10g_fifo_del port (10GBASE‑R) On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_del port. This signal is asserted when a word is deleted from the RX FIFO. This signal is only used for the 10GBASE‑R protocol.
Enable rx_10g_fifo_insert port (10GBASE‑R) On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_insert port. This signal is asserted when a word is inserted into the RX FIFO. This signal is only used for the 10GBASE‑R protocol.
Enable rx_10g_fifo_rd_en port (Interlaken) On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_rd_en input port. Asserting this signal reads a word from the RX FIFO. This signal is only available for the Interlaken protocol.
Enable rx_10g_fifo_align_val port (Interlaken) On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_align_val output port. This signal is asserted when the word alignment pattern is found. This signal is only available for the Interlaken protocol.
enable rx10g_clk33out port On/Off When you turn this option On, the 10G PCS includes a divide by 33 clock output port. You typically need this option when the fabric to PCS interface width is 66.
Enable rx_10g_fifo_align_clr port (Interlaken) On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_align_clr input port. When this signal is asserted, the FIFO resets and begins searching for a new alignment pattern. This signal is only available for the Interlaken protocol.
Enable rx_10g_fifo_align_en port (Interlaken) On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_align_en input port. This signal is used for FIFO deskew for Interlaken. When asserted, the corresponding channel is enabled for alignment. This signal is only available for the Interlaken protocol.

Interlaken Frame Generator

TX Frame generator generates the metaframe. It encapsulates the payload from MAC with the framing layer control words, including sync, scrambler, skip and diagnostic words. The following table describes the Interlaken frame generator parameters.

Table 275.  Interlaken Frame Generator Parameters
Parameter Range Description
teng_tx_framgen_enable On/Off When you turn this option On, the frame generator block of the 10G PCS is enabled.
teng_tx_framgen_user_length 0-8192 Specifies the metaframe length.
teng_tx_framgen_burst_enable On/Off When you turn this option On, the frame generator burst functionality is enabled.
Enable tx_10g_frame port On/Off When you turn this option On, the 10G PCS includes the tx_10g_frame output port. When asserted, tx_10g_frame indicates the beginning of a new metaframe inside the frame generator.
Enable tx_10g_frame_diag_status port On/Off When you turn this option On, the 10G PCS includes the tx_10g_frame_diag_status 2‑bit input port. This port contains the lane Status Message from the framing layer Diagnostic Word, bits[33:32]. This message is inserted into the next Diagnostic Word generated by the frame generation block. The message must be held static for 5 cycles before and 5 cycles after the tx_frame pulse.
Enable tx_10g_frame_burst_en port On/Off When you turn this option On, the 10G PCS includes the tx_10g_frame_burst_en input port. This port controls frame generator data reads from the TX FIFO. The value of this signal is latched once at the beginning of each Metaframe. It controls whether data is read from the TX FIFO or SKIP Words are inserted for the current Metaframe. It must be held static for 5 cycles before and 5 cycles after the tx_frame pulse. When tx_10g_frame_burst_en is 0, the frame generator does not read data from the TX FIFO for current Metaframe. It insert SKIPs. When tx_10g_frame_burst_en is 1, the frame generator reads data from the TX FIFO for current Metaframe.

Interlaken Frame Synchronizer

The Interlaken frame synchronizer block achieves lock by looking for four synchronization words in consecutive metaframes. After synchronization, the frame synchronizer monitors the scrambler word in the metaframe and deasserts the lock signal after three consecutive mismatches and starts the synchronization process again. Lock status is available to the FPGA fabric. The following table describes the Interlaken frame synchronizer parameters.

Table 276.  Interlaken Frame Synchronizer Parameters
Parameter Range Description
teng_tx_framsync_enable On/Off When you turn this option On, the 10G PCS frame generator is enabled.
Enable rx_10g_frame port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame output port. This signal is asserted to indicate the beginning of a new metaframe inside.
Enable rx_10g_frame_lock_port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_lock output port. This signal is asserted to indicate that the frame synchronization state machine has achieved frame lock.
Enable rx_10g_frame_mfrm_err port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_mfrm_err output port. This signal is asserted to indicate an metaframe error.
Enable rx_10g_frame_sync_err port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_sync_err output port. This signal is asserted to indicate synchronization control word errors. This signal remains asserted during the loss of block_lock and does not update until block_lock is recovered.
Enable rx_10g_frame_skip_ins port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_skip_ins output port. This signal is asserted to indicate a SKIP word was received by the frame sync in a non‑SKIP word location within the metaframe.
Enable rx_10g_frame_pyld_ins port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_pyld_ins output port. This signal is asserted to indicate a SKIP word was not received by the frame sync in a SKIP word location within the metaframe.
Enable rx_10g_frame_skip_err port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_skip_err output port. This signal is asserted to indicate the frame synchronization has received an erroneous word in a Skip control word location within the Metaframe. This signal remains asserted during the loss of block_lock and does update until block_lock is recovered.
Enable rx_10g_frame_diag_err port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_diag_err output port. This signal is asserted to indicate a diagnostic control word error. This signal remains asserted during the loss of block_lock and does update until block_lock is recovered.
Enable rx_10g_frame_diag_status port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_diag_status 2‑bit output port per channel. This port contains the lane Status Message from the framing layer Diagnostic Word, bits[33:32]. This message is inserted into the next Diagnostic Word generated by the frame generation block.

Interlaken CRC32 Generator and Checker

CRC-32 provides a diagnostic tool on a per-lane basis. You can use CRC-32 to trace interface errors back to an individual lane. The CRC-32 calculation covers the whole metaframe including the Diagnostic Word itself. This CRC code value is stored in the CRC32 field of the Diagnostic Word. The following table describes the CRC-32 parameters.

Table 277.  Interlaken CRC32 Generator and Checker Parameters
Parameter Range Description
Enable Interlaken TX CRC32 Generator On/Off When you turn this option On, the TX 10G PCS datapath includes the CRC32 function.
Enable Interlaken RX CRC32 Generator On/Off When you turn this option On, the RX 10G PCS datapath includes the CRC32 function.
Enable rx_10g_crc32_err port On/Off When you turn this option On, the 10G PCS includes the rx_10g_crc32_err port. This signal is asserted to indicate that the CRC checker has found an error in the current metaframe.

10GBASE-R BER Checker

The BER monitor block conforms to the 10GBASE-R protocol specification as described in IEEE 802.3-2008 Clause-49. After block lock is achieved, the BER monitor starts to count the number of invalid synchronization headers within a 125-ms period. If more than 16 invalid synchronization headers are observed in a 125-ms period, the BER monitor provides the status signal to the FPGA fabric, indicating a high bit error. The following table describes the 10GBASE-R BER checker parameters.

Table 278.  10GBASE-R BER Checker Parameters
Parameter Range Description
Enable rx_10g_highber port (10GBASE‑R) On/Off When you turn this option On, the TX 10G PCS datapath includes the rx_10g_highber output port. This signal is asserted to indicate a BER of >10 4 . A count of 16 errors in 125‑ m s period indicates a BER > 10 4 . This signal is only available for the 10GBASE‑R protocol.
Enable rx_10g_highber_clr_cnt port (10GBASE‑R) On/Off When you turn this option On, the TX 10G PCS datapath includes the rx_10g_highber_clr_cnt input port. When asserted, the BER counter resets to 0. This signal is only available for the 10GBASE‑R protocol.
Enable rx_10g_clr_errblk_count port (10GBASE‑R) On/Off When you turn this option On, the 10G PCS includes the rx_10g_clr_errblk_count input port. When asserted, error block counter that counts the number of RX errors resets to 0. This signal is only available for the 10GBASE‑R protocol.

64b/66b Encoder and Decoder

The 64b/66b encoder and decoder conform to the 10GBASE-R protocol specification as described in IEEE 802.3-2008 Clause-49. The 64b/66b encoder sub-block receives data from the TX FIFO and encodes the 64-bit data and 8-bit control characters to the 66-bit data block required by the 10GBASE-R protocol. The transmit state machine in the 64b/66b encoder sub-block checks the validity of the 64-bit data from the MAC layer and ensures proper block sequencing.

The 64b/66b decoder sub-block converts the received data from the descrambler into 64-bit data and 8-bit control characters. The receiver state machine sub-block monitors the status signal from the BER monitor. The following table describes the 64/66 encoder and decoder parameters.

Table 279.  64b/66b Encoder and Decoder Parameters
Parameter Range Description
Enable TX sync header error insertion On/Off When you turn this option On, the 10G PCS records. This parameter is valid for the Interlaken and 10GBASE‑R protocols.
Enable TX 64b/66b encoder On/Off When you turn this option On, the 10G PCS includes the TX 64b/66b encoder.
Enable TX 64b/66b encoder On/Off When you turn this option On, the 10G PCS includes the RX 64b/66b decoder.

Scrambler and Descrambler Parameters

TX scrambler randomizes data to create transitions to create DC-balance and facilitate CDR circuits based on the x58 + x39 +1 polynomial. The scrambler operates in the following two modes:

  • Synchronous—The Interlaken protocol requires synchronous mode.
  • Asynchronous (also called self-synchronized)—The 10GBASE-R protocol requires this mode as specified in IEEE 802.3-2008 Clause-49.

The descrambler block descrambles received data to regenerate unscrambled data using the x58+x39+1 polynomial. The following table describes the scrambler and descrambler parameters.

Table 280.  Scrambler and Descrambler Parameters
Parameter Range Description
Enable TX scrambler On/Off When you turn this option On, the TX 10G PCS datapath includes the scrambler function. This option is available for the Interlaken and 10GBASE‑R protocols.
TX scrambler seed User‑specified 15-bit value You must provide a different seed for each lane. This parameter is only required for the Interlaken protocol.
Enable RX scrambler On/Off When you turn this option On, the RX 10G PCS datapath includes the scrambler function. This option is available for the Interlaken and 10GBASE‑R protocols.
Enable rx_10g_descram_err port On/Off When you turn this option On, the 10G PCS includes the rx_10g_descram_err port.

Interlaken Disparity Generator and Checker

The Disparity Generator monitors the data transmitted to ensure that the running disparity remains within a ±96-bit bound. It adds the 67th bit to indicate whether or not the data is inverted. The Disparity Checker monitors the status of the 67th bit of the incoming word to determine whether or not to invert bits[63:0] of the received word. The following table describes Interlaken disparity generator and checker parameters.

Table 281.  Interlaken Disparity Generator and Checker Parameters
Parameter Range Description
Enable Interlaken TX disparity generator On/Off When you turn this option On, the 10G PCS includes the disparity generator. This option is available for the Interlaken protocol.
Enable Interlaken RX disparity generator On/Off When you turn this option On, the 10G PCS includes the disparity checker. This option is available for the Interlaken protocol.

Block Synchronization

The block synchronizer determines the block boundary of a 66-bit word for the 10GBASE-R protocol or a 67-bit word for the Interlaken protocol. The incoming data stream is slipped one bit at a time until a valid synchronization header (bits 65 and 66) is detected in the received data stream. After the predefined number of synchronization headers is detected, the block synchronizer asserts rx_10g_blk_lock to other receiver PCS blocks down the receiver datapath and to the FPGA fabric. The block synchronizer is designed in accordance with both the Interlaken protocol specification and the 10GBASE-R protocol specification as described in IEEE 802.3-2008 Clause-49.

Table 282.  Bit Reversal and Polarity Inversion Parameters
Parameter Range Description
Enable RX block synchronizer On/Off When you turn this option On, the 10G PCS includes the RX block synchronizer. This option is available for the Interlaken and 10GBASE‑R protocols.
Enable rx_10g_blk_lock port On/Off When you turn this option On, the 10G PCS includes the rx_10G_blk_lock output port. This signal is asserted to indicate the receiver has achieved block synchronization. This option is available for the Interlaken, 10GBASE‑R, and other protocols that user the PCS lock state machine to achieve and monitor block synchronization.
Enable rx_10g_blk_sh_err port On/Off When you turn this option On, the 10G PCS includes the rx_10G_blk_sh_err output port. This signal is asserted to indicate that an invalid sync header has been received. This signal is active after block lock is achieved. This option is available for the Interlaken, 10GBASE‑R, and other protocols that user the PCS lock state machine to achieve and monitor block synchronization.

Gearbox

The gearbox adapts the PMA data width to a wider PCS data width when the PCS is not two or four times the PMA width.

Table 283.  Gearbox Parameters
Parameter Range Description
Enable TX data polarity inversion On/Off When you turn this option On, the gearbox inverts the polarity of TX data allowing you to correct incorrect placement and routing on the PCB.
Enable TX data bitslip On/Off When you turn this option On, the TX gearbox operates in bitslip mode.
Enable RX data polarity inversion On/Off When you turn this option On, the gearbox inverts the polarity of RX data allowing you to correct incorrect placement and routing on the PCB.
Enable RX data bitslip On/Off When you turn this option On, the 10G PCS RX block synchronizer operates in bitslip mode.
Enable tx_10g_bitslip port On/Off When you turn this option On, the 10G PCS includes the tx_10g_bitslip input port. The data slips 1 bit for every positive edge of the tx_10g_bitslip input. The maximum shift is < pcswidth> -1 bits, so that if the PCS is 64 bits wide, you can shift 0-63 bits.
Enable rx_10g_bitslip port On/Off When you turn this option On, the 10G PCS includes the rx_10g_bitslip input port. The data slips 1 bit for every positive edge of the rx_10g_bitslip input. he maximum shift is < pcswidth> -1 bits, so that if the PCS is 64 bits wide, you can shift 0-63 bits.

PRBS Verifier

You can use the PRBS pattern generators for verification or diagnostics. The pattern generator blocks support the following patterns:

  • Pseudo-random binary sequence (PRBS)
  • Pseudo-random pattern
  • Square wave
Table 284.  PRBS Parameters
Parameter Range Description
Enable rx_10g_prbs ports On/Off When you turn this option On, the PCS includes the rx_10g_prbs_done , rx_10g_prbs_err and rx_10g_prbs_err_clrsignals to provide status on PRBS operation.

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