V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

19.3. Transceiver PLL Signals

Figure 108. Transceiver PLL Top-Level Signals The following figure illustrates the top-level signals of the Transceiver PLL which are defined in the table below.
Signal Name Direction Description
pll_powerdown Input When asserted, powers down the PLL.
pll_refclk Input Input reference clock for the CMU PLL.
pll_fbclk Input The feedback input port for the PLL.
pll_clkout Output Output clock from the PLL.
pll_locked Output When asserted, indicates that the PLL has locked to the input reference clock.
reconfig_to_xcvr[69:0] Input

Reconfiguration signals from the Transceiver Reconfiguration Controller. When you enable the reconfiguration bus, the simulation model for the TX PLL supports dynamic reconfiguration. When you enable this bus, the Intel® Quartus® Prime software does not merge TX PLL by default; however, you can merge TX PLLs using QSF settings.

reconfig_from_xcvr[45:0] Output Reconfiguration signals to the Transceiver Reconfiguration Controller.

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