V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

10.2. Performance and Resource Utilization

Because the PCS and PMA are both implemented in hard logic, the Custom PHY IP Core requires less than 1% of FPGA resources.
Table 123.  Custom PHY IP Core Performance and Resource Utilization—Stratix V GT Device
Channels Combinational ALUTs Logic Registers (Bits)
1 142 154
4 244 364

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