V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

6.1.4. Resource Utilization

The following estimates are obtained by compiling the PHY IP core with the Intel® Quartus® Prime software.

Table 71.  Resource Utilization
Device Speed ALMs ALUTs Logic Registers Memory Block
Arria® V 1G/2.5G 550 750 1200 2 (M10K)
1G/2.5G with IEEE 1588v2 enabled 1200 1850 2550 2 (M10K)

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