V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

21.5. Differences Between PHY IP Core for PCIe PHY (PIPE) Ports for Stratix IV and Stratix V Devices

This section lists the differences between the top-level signals in Stratix IV GX and Stratix V GX/GS devices. PIPE standard ports remain, but are now prefixed with pipe_. Clocking options are simplified to match the PIPE 2.0 specification.
Table 358.  PCIe PHY (PIPE) Correspondence between Stratix IV GX Device and Stratix V Device Signals
Stratix IV GX Device Signal Name22 Stratix V GX Device Signal Name Width
 Reference Clocks and Resets
pll_inclk pll_ref_clk 1
rx_cruclk Not available [<n> -1:0]
tx_coreclk Not available [<n> -1:0]
rx_coreclk Not available [<n> -1:0]
tx_clkout/coreclkout pipe_pclk 1
pll_powerdown These signals are now available as control and status registers. Refer to the "Avalon-MM PHY Management Interface and PCI Express PHY (PIPE) IP Core Registers". 1
cal_blk_powerdown 1
Not available tx_ready (reset control status) 1
Not available rx_ready (reset curl status) 1
PIPE interface Ports
tx_datain pipe_txdata [<n><d>-1:0]
tx_ctrlenable pipe_txdatak [(<d>/8)*<n>-1:0]
tx_detectrxloop pipe_txdetectrx_loopback [<n> -1:0]
tx_forcedispcompliance pipe_txcompliance [<n> -1:0]
tx_forceelecidle pipe_txelecidle [<n> -1:0]
txswing pipe_txswing [<n> -1:0]
tx_pipedeemph[0] pipe_txdeemph [<n> -1:0]
tx_pipemargin[2:0] pipe_txmargin [3<n>-1:0]
rateswitch[0] pipe_rate[1:0] [<n>-1:0]
powerdn pipe_powerdown [2<n>-1:0]
rx_elecidleinfersel pipe_eidleinfersel [3<n>-1:0]
rx_dataout pipe_rxdata [<n>-*<d>-1:0]
rx_ctrldetect pipe_rxdatak [(<d>/8)*<n>-1:0]
pipedatavalid pipe_rxvalid [<n>-1:0]
pipe8b10binvpolarity pipe_rxpolarity [<n>-1:0]
pipeelecidle pipe_rxelecidle [<n>-1:0]
pipephydonestatus pipe_phystatus [<n>-1:0]
pipestatus pipe_rxstatus [3<n>-1:0]
 Non-PIPE Ports
rx_pll_locked rx_is_lockedtoref [<n>--1:0]
rx_freqlocked rx_is_lockedtodata [<n>--1:0]
pll_locked pll_locked 1
rx_syncstatus rx_syncstatus (also management interface) [(<d>/8)*<n>-1:0]
rx_locktodata These signals are now available as control and status registers. Refer to the “Register Interface and Register Descriptions”. [<n>-1:0]
rx_locktorefclk [<n>-1:0]
tx_invpolarity [<n>-1:0]
rx_errdetect [(<d>/8)*<n>-1:0]
rx_disperr [(<d>/8)*<n>-1:0]
rx_patterndetect [(<d>/8)*<n>-1:0]
tx_phase_comp_fifo_error [<n>-1:0]
rx_phase_comp_fifo_error [<n>-1:0]
rx_signaldetect [<n>-1:0]
rx_rlv [<n>-1:0]
rx_datain rx_serial_data [<n>-1:0]
tx_dataout tx_serial_data [<n>-1:0]
cal_blk_clk These signals are included in the reconfig_to_xcvr bus 1
reconfig_clk 1
fixedclk 1
reconfig_togxb reconfig_to_xcvr Variable
reconfig_fromgxb reconfig_from_xcvr Variable
Avalon MM Management Interface
Not available phy_mgmt_clk_reset 1
phy_mgmt_clk 1
phy_mgmt_address [8:0]
phy_mgmt_read 1
phy_mgmt_readdata [31:0]
phy_mgmt_write 1
phy_mgmt_writedata [31:0]
22 <n> = the number of lanes. <d> = the total deserialization factor from the pin to the FPGA fabric.

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