V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

16.6.5. Rate Match FIFO

The rate match FIFO compensates for the very small frequency differences between the local system clock and the RX recovered clock.
For more information refer to the Rate Match FIFO sections in the Transceiver Architecture in Cyclone V Devices.
Table 306.  Rate Match FIFO Parameters

Parameter

Range

Description

Enable RX rate match FIFO

On/Off

When you turn this option On, the PCS includes a FIFO to compensate for the very small frequency differences between the local system clock and the RX recovered clock.

RX rate match insert/delete +ve pattern (hex)

User-specified 20 bit pattern

Specifies the +ve (positive) disparity value for the RX rate match FIFO as a hexadecimal string.

RX rate match insert/delete -ve pattern (hex)

User-specified 20 bit pattern

Specifies the -ve (negative) disparity value for the RX rate match FIFO as a hexadecimal string.

When you enable the simplified data interface and enable the rate match FIFO status ports, the rate match FIFO bits map to the high-order bits of the data bus as listed in the following table. This table uses the following definitions:

  • Basic double width: The Standard PCS protocol mode GUI option is set to basic. The FPGA data width is twice the PCS data width to allow the fabric to run at half the PCS frequency.
  • SerialTM RapidIO double width: You are implementing the Serial RapidIO protocol. The FPGA data width is twice the PCS data width to allow the fabric to run at half the PCS frequency.
Note: If you have the auto-negotiation state machine in your transceiver design, please note that the rate match FIFO is capable of inserting or deleting the first two bytes (K28.5//D2.2) of /C2/ ordered sets during auto-negotiation. However, the insertion or deletion of the first two bytes of /C2/ ordered sets can cause the auto-negotiation link to fail. For more information, visit Intel Knowledge Base Support Solution.
Table 307.  Status Flag Mappings for Simplified Native PHY Interface
Status Condition Protocol Mapping of Status Flags to RX Data Value
Full PHY IP Core for PCI Express (PIPE)

Basic double width

RXD[62:62] = rx_rmfifostatus[1:0], or

RXD[46:45] = rx_rmfifostatus[1:0], or

RXD[30:29] = rx_rmfifostatus[1:0], or

RXD[14:13] = rx_rmfifostatus[1:0]

2'b11 = full
XAUI, GigE, Serial RapidIO double width rx_std_rm_fifo_full 1'b1 = full
All other protocols Depending on the FPGA fabric to PCS interface width either:

RXD[46:45] = rx_rmfifostatus[1:0], or

RXD[14:13] = rx_rmfifostatus[1:0]

2'b11 = full
Empty PHY IP Core for PCI Express (PIPE)

Basic double width

RXD[62:62] = rx_rmfifostatus[1:0], or

RXD[46:45] = rx_rmfifostatus[1:0], or

RXD[30:29] = rx_rmfifostatus[1:0], or

RXD[14:13] = rx_rmfifostatus[1:0]

(2'b10) AND (PAD or EDB)

PAD = K23.7 or 9'h1F7

EDB = K30.7 or 9'h1FE

XAUI, GigE, Serial RapidIO double width rx_std_rm_fifo_empty 1'b1 = empty
All other protocols Depending on the FPGA fabric to PCS interface width either:

RXD[46:45] = rx_rmfifostatus[1:0], or

RXD[14:13] = rx_rmfifostatus[1:0]

(2'b10) AND (PAD or EDB) 16

PAD = K23.7 or 9'h1F7

EDB = K30.7 or 9'h1FE

Insertion Basic double width

Serial RapidIO double width

RXD[62:62] = rx_rmfifostatus[1:0], or

RXD[46:45] = rx_rmfifostatus[1:0], or

RXD[30:29] = rx_rmfifostatus[1:0], or

RXD[14:13] = rx_rmfifostatus[1:0]

2'b10
All other protocols Depending on the FPGA fabric to PCS interface width either:

RXD[46:45] = rx_rmfifostatus[1:0], or

RXD[14:13] = rx_rmfifostatus[1:0]

2'b10
Deletion Basic double width

Serial RapidIO double width

RXD[62:62] = rx_rmfifostatus[1:0], or

RXD[46:45] = rx_rmfifostatus[1:0], or

RXD[30:29] = rx_rmfifostatus[1:0], or

RXD[14:13] = rx_rmfifostatus[1:0]

2'b01
All other protocols Depending on the FPGA fabric to PCS interface width either:

RXD[46:45] = rx_rmfifostatus[1:0], or

RXD[14:13] = rx_rmfifostatus[1:0]

2'b01
16 PAD and EBD are control characters. PAD character is typically used fo fill in the remaining lanes in a multi-lane link when one of the link goes to logical idle state. EDB indicates End Bad Packet.

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