3.7. General Option Parameters
This section describes the 10GBASE-R PHY parameters, which you can set using the MegaWizard Plug-In Manager.
Arria V GZ
Stratix IV GT
|Specifies the target device.|
|Number of channels||1-32||The total number of 10GBASE-R PHY channels.|
|Mode of operation||
|Arria V and Stratix V devices allow duplex, TX, or RX mode. Stratix IV GT devices only support duplex mode.|
|PLL type||CMU, ATX||
For Arria V GZ, Stratix IV, and Stratix V devices:
You can select either the CMU or ATX PLL. The CMU PLL has a larger frequency range than the ATX PLL. The ATX PLL is designed to improve jitter performance and achieves lower channel-to-channel skew. Another advantage of the ATX PLL is that it does not use a transceiver channel, while the CMU PLL does.
Altera recommends the ATX PLL for data rates <= 8 Gbps.
|Reference Clock Frequency||
|Arria V and Stratix V devices support both frequencies. Stratix IV GT devices only support 644.53125 MHz.|
|PCS / PMA interface width||
|For Stratix V and Arria V GZ devices only:
Specifies the data interface width between the 10G PCS and the transceiver PMA. Smaller width corresponds to lower PCS latency but higher frequency.
32 bit PCS / PMA interface with does not support data rates up to 10.3125 Gbps in C4/I4 Arria V GZ device variants. Refer to Arria V GZ Device Datasheet for details on data rates supported by different device variants.
|Enable additional control and status pins||On/Off||If you turn this option On, the following 2 signals are brought out to the top level of the IP core to facilitate debugging: rx_hi_ber and rx_block_lock.|
|Enable rx_recovered_clk pin||On/Off||When you turn this option On, the RX recovered clock signal is an output signal.|
|Enable pll_locked status port||On/Off||
For Arria V and Stratix V devices:
When you turn this option On, a PLL locked status signal is included as a top-level signal of the core.
|Use external PMA control and reconfig||On/Off||
For Stratix IV devices:
If you turn this option on, the PMA controller and reconfiguration block are external, rather than included in the 10GBASE-R PHY IP Core, allowing you to use the same PMA controller and reconfiguration IP cores for other protocols in the same transceiver quad.
When you turn this option On, the cal_blk_powerdown (0x021) and pma_tx_pll_is_locked (0x022) registers are available.
|Enable rx_coreclkin port||On/Off||When selected, rx_coreclkin is sourced from the 156.25 MHz xgmii_rx_clk signal avoiding the use of a FPLL to generate this clock. This clock drives the read side of RX FIFO.|
|Enable embedded reset control||On/Off||When On, the automatic reset controller initiates the reset sequence for the transceiver. When Off you can design your own reset logic using tx_analogreset , rx_analogreset, tx_digitalreset, rx_digitalreset, and pll_powerdown which are top‑level ports of the Custom Transceiver PHY. You may also use the Transceiver PHY Reset Controller to reset the transceivers. For more information, refer to the Transceiver Reconfiguration Controller IP Core . By default, the CDR circuitry is in automatic lock mode whether you use the embedded reset controller or design your own reset logic. You can switch the CDR to manual mode by writing the pma_rx_setlocktodata or pma_rx_set_locktoref registers to 1. If either the pma_rx_set_locktodata and pma_rx_set_locktoref is set, the CDR automatic lock mode is disabled.|
|Starting channel number||0-96||
For Stratix IV devices, specifies the starting channel number. Must be 0 or a multiple of 4. You only need to set this parameter if you are using external PMA and reconfiguration modules.
In Stratix V devices, by default, the logical channel 0 is assigned to either physical transceiver channel 1 or channel 4 of a transceiver bank. However, if you have already created a PCB with a different lane assignment for logical channel 0, you can use the work around shown in the example below.
Assignment of the starting channel number is required for serial transceiver dynamic reconfiguration.
|Enable IEEE 1588 latency adjustment ports||On/Off||When you turn this option On, the core includes logic to implement the IEEE 1588 Precision Time Protocol.|
Changing the Default Logical Channel 0 Channel Assignments in Stratix V Devices for ×6 or ×N Bonding
set_parameter -name pma_bonding_master "\"1\"" -to "<PHY IP instance name>"
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