V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

8.8. Interlaken PHY Avalon-ST RX Interface

This section lists the signals in the Avalon-ST RX interface.
Table 103.  Avalon-ST RX Signals
Signal Name Direction Description
rx_parallel_data<n>[63:0] Output Avalon-ST data bus driven from the RX PCS to the FPGA fabric. This output is synchronous to the rx_coreclkin clock domain.
rx_parallel_data<n>[64] Output

When asserted, indicates that rx_parallel_data<n>[63:0] is valid. When deasserted, indicates the rx_parallel_data<n>[63:0] is invalid. This output is synchronous to the rx_coreclkin clock domain.

The Interlaken PCS implements a gearbox between the PMA and PCS interface. The rx_parallel_data<n>[64] port is deasserted whenever the gearbox is in the invalid region. The Interlaken MAC should not read rx_parallel_data<n>[65, 63:0] if rx_parallel_data<n>[64] is deasserted.

rx_parallel_data<n>[65] Output

Indicates whether rx_parallel_data<n>[63:0] represents control or data. When deasserted, rx_parallel_data<n>[63:0] is a data word. When asserted, rx_paralleldata<n>[63:0] is a control word. This output is synchronous to the rx_coreclkin clock domain.

The value of header synchronization bits[65:64] of the Interlaken word identify whether bits[63:0] are Framing Layer Control/Burst/IDLE Word or a data word. The value 2’b10 indicating a Framing Layer Control/Burst/IDLE Word is gray encoded to the value 1’b1 and rx_parallel_data<n>[65] is asserted by the Interlaken Receive PCS. The value 2’b01 indicating data word is gray encoded to the value 1’b0 and rx_parallel_data<n>[65] is deasserted by the Interlaken Receive PCS. The Framing Layer Control Words (Frame Sync, Scrambler State, Skip, and Diag) are not discarded but are modified (scrambler seed cleared to 0) and sent to the Interlaken MAC for multi-lane alignment and deskew on the lanes.

rx_parallel_data<n>[66] Output

This is an active-high synchronous status signal indicating that block lock (frame synchronization) and frame lock (metaframe boundary delineation) have been achieved. The Interlaken MAC must use this signal to indicate that Metaframe synchronization has been achieved for this lane. You must use this rx_parallel_data[66] as the primary frame synchronization status flag and only use the optional rx_parallel_data[70] as the secondary frame synchronization status flag. This output is synchronous to the rx_coreclkin clock domain.

If the RX PCS FIFO reaches the empty state or is in an empty state, rx_parallel_data<n>[66] Block Lock and Frame Lock status signals are deasserted in the next clock cycle. rx_parallel_data<n>[70] indicating metaframe lock and rx_parallel_data<n>[69] indicating that the first Interlaken synchronization word alignment pattern has been received remain asserted.

rx_parallel_data<n>[67] Output When asserted, indicates an RX FIFO overflow error.
rx_parallel_data<n>[68] Output When asserted, indicates that the RX FIFO is partially empty and is still accepting data from the frame synchronizer. This signal is asserted when the RX FIFO fill level is below the rx_fifo_pempty threshold. This output is synchronous to the rx_coreclkin clock domain. To prevent underflow, the Interlaken MAC should begin reading from the RX FIFO when this signal is deasserted, indicating sufficient FIFO contents (RX FIFO level above rx_fifo_pempty threshold). The MAC should continue to read the RX FIFO to prevent overflow as long as this signal is not reasserted. You can assert a FIFO flush using the rx_fifo_clr<n> when the receive FIFO overflows. This output is synchronous to the rx_clkout clock domain. Therefore, you must synchronize rx_parallel_data<n>[68] to the rx_coreclkin before making the assignment below.

You can tie this signal's inverted logic to the rx_dataout_bp<n> receive FIFO read enable signal as the following assignment statement illustrates:

assign rx_dataout_bp[0] =!(rx_parallel_data[68]);

rx_parallel_data<n>[69] Output

When asserted, indicates that the RX FIFO has found the first Interlaken synchronization word alignment pattern. For very short metaframes, this signal may be asserted after the frame synchronizer state machine validates frame synchronization and asserts rx_parallel_data<n>[70] because this signal is asserted by the RX FIFO which is the last PCS block in the RX datapath. This output is synchronous to the rx_coreclkin clock domain.

This signal is optional. If the RX PCS FIFO reaches the empty state or is in an empty state, rx_parallel_data<n>[70] indicating metaframe lock and rx_parallel_data<n>[69] indicating that the first Interlaken synchronization word alignment pattern has been received remain asserted, but rx_parallel_data<n>[66] block lock and frame lock status signal are deasserted in the next clock cycle.

rx_parallel_data<n>[70] Output

When asserted, indicates that the RX frame synchronization state machine has found and received 4 consecutive, valid synchronization words. The frame synchronization state machine requires 4 consecutive synchronization words to exit the presync state and enter the synchronized state. You should only use this optional signal as a secondary status flag. The rx_parallel_data[66] signal should be used as the primary frame synchronization status flag. This output is synchronous to the rx_clkout clock domain.

This signal is optional. If the RX PCS FIFO reaches an empty state or is in an empty state, rx_parallel_data<n>[70] indicating metaframe lock and rx_parallel_data<n>[69] indicating that the first Interlaken synchronization word alignment pattern has been received remain asserted but rx_parallel_data<n>[66] block lock and frame lock status signal are deasserted in the next clock cycle.

rx_parallel_data<n>[71] Output When asserted, indicates a CRC32 error in this lane. This signal is optional. This output is synchronous to the rx_clkout clock domain.
rx_ready Output When asserted, indicates that the RX interface has exited the reset state and is ready for service. The Interlaken MAC must wait for rx_ready to be asserted before initiating data transfer on any lanes. This output is synchronous to the phy_mgmt_clk domain.
rx_clkout Output Output clock from the RX PCS. The frequency of this clock equals the Lane rate divided by 40, which is the PMA serialization factor.
rx_fifo_clr<n> Input

When asserted, the RX FIFO is flushed. This signal allows you to clear the FIFO if the receive FIFO overflows or if the Interlaken MAC is not able to achieve multi-lane alignment in the Interlaken MAC's deskew state machine. The rx_fifo_clr signal must be asserted for 4 rx_clkout cycles to successfully flush the RX FIFO.

This output is synchronous to the rx_clkout clock domain.

rx_dataout_bp<n> Input

When asserted, enables reading of data from the RX FIFO. This signal functions as a read enable. The RX interface has a ready latency of 1 cycle so that rx_paralleldata<n>[63:0] and rx_paralleldata<n>[65] are valid the cycle after rx_dataout_bp<n> is asserted.

In multi-lane configurations, the rx_dataout_bp<n> port signals must not be logically tied together.

This output is synchronous to the rx_coreclkin clock domain. You can tie this rx_dataout_bp<n> RX FIFO read enable signal to the inverted logic of the rx_parallel_data[68] RX FIFO partially empty signal using the following assignment statement:

assign rx_dataout_bp[0] =! (rx_parallel_data[68]);

rx_user_clkout Output Master channel rx_user_clkout is available when you do not create the optional rx_coreclkin.

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