9.13. PHY for PCIe (PIPE) Link Equalization for Gen3 Data Rate
“Section 4.2.3 Link Equalization Procedure for 8.0 GT/s Data Rate” in the PCI Express Base Specification, Rev. 3.0 provides detailed information about the four-stage link equalization procedure. A new LTSSM state, Recovery.Equalization with Phases 0–3, reflects progress through Gen3 equalization. Phases 2 and 3 of link equalization are optional; however, the link must progress through all four phases, even if no adjustments occur. Skipping Phases 2 and 3 speeds up link training at the expense of link BER optimization.