V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

7.6. XAUI PHY General Parameters

This section describes the settings available on General Options tab.
General Options
Name Value Description
Device family

Arria II GX

Arria V

Arria V GZ

Cyclone IV GX

Cyclone V

HardCopy IV

Stratix IV

Stratix V

The target device family.
Starting channel number 0-124

The physical starting channel number in the Altera device for channel 0 of this XAUI PHY. In Arria II GX, Cyclone IV GX, HardCopy IV, and Stratix IV devices, this starting channel number must be 0 or a multiple of 4.

In Arria V GZ and Stratix V devices, logical lane 0 should be assigned to either physical transceiver channel 1 or channel 4 of a transceiver bank. However, if you have already created a PCB with a different lane assignment for logical lane 0, you can use the workaound shown in Overriding Logical Lane 0 Channel Assignment Restrictions in Stratix V Devices to remove this restriction.

Assignment of the starting channel number is required for serial transceiver dynamic reconfiguration. Check logical channel 0 restrictions in Cyclone 5 and Arria 5.

XAUI interface type

Hard XAUI

Soft XAUI

DDR XAUII

The following 3 interface types are available:

  • Hard XAUI–Implements the PCS and PMA in hard logic. Available for Arria II, Cyclone IV, HardCopy IV, and Stratix IV devices.
  • Soft XAUI–Implements the PCS in soft logic and the PMA in hard logic. Available for HardCopy IV, Stratix IV, Arria V, Cyclone V, and Stratix V devices.
  • DDR XAUI–Implements the PCS in soft logic and the PMA in hard logic. Both the application and serial interfaces run at twice the frequency of the Soft XAUI options. Available for HardCopy IV Stratix IV devices.

All interface types include 4 channels.

Data rate Device Dependent Specifies the data rate.
PLL type

CMU

ATX

You can select either the CMU or ATX PLL. The CMU PLL has a larger frequency range than the ATX PLL. The ATX PLL is designed to improve jitter performance and achieves lower channel-to-channel skew; however, it supports a narrower range of data rates and reference clock frequencies. Another advantage of the ATX PLL is that it does not use a transceiver channel, while the CMU PLL does. This parameter is available for the soft PCS and DDR XAUI.

The ATX PLL is not available for all devices.

Base data rate

1 × Lane rate

2 × Lane rate

4 × Lane rate

The base data rate is the frequency of the clock input to the PLL. Select a base data rate that minimizes the number of PLLs required to generate all the clock s required for data transmission. By selecting an appropriate base data rate, you can change data rates by changing the divider used by the clock generation block. This parameter is available for Stratix V devices.
Number of XAUI interfaces 1 Specifies the number of XAUI interfaces. Only 1 is available in the current release.

Overriding Logical Lane 0 Channel Assignment Restrictions in Stratix V Devices shows how to remove the restriction on logical lane 0 channel assignment in Stratix V devices by redefining the pma_bonding_master parameter using the Intel® Quartus® Prime Assignment Editor. In this example, the pma_bonding_master was originally assigned to physical channel 1. (The original assignment could also have been to physical channel 4.) The to parameter reassigns the pma_bonding_master to the XAUI instance name shown in quotation marks. You must substitute the instance name from your design for the instance name shown in quotation marks

Overriding Logical Lane 0 Channel Assignment Restrictions in Stratix V Devices

set_parameter -name pma_bonding_master "\"1\"" -to "<xaui 
instance name>|sv_xcvr_xaui:alt_xaui_phy|sv_xcvr_low_latency_phy_nr:
alt_pma_0|sv_xcvr_custom_native:sv_xcvr_custom_inst|sv_xcvr_native:
gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst"

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