V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

17.15. Transceiver Reconfiguration Controller PLL Reconfiguration Registers

Lists the PLL reconfiguration registers that you can access using Avalon-MM read and write commands on reconfiguration management interface.
Note: All undefined register bits are reserved.
Table 335.   PLL Reconfiguration Registers
Reconfig Addr Bits R/W Register Name Description
7’h40 [9:0] RW logical channel number

The logical channel number. Must be specified when performing dynamic updates. The Transceiver Reconfiguration Controller maps the logical address to the physical address.

When reconfiguring the reference clock for the TX PLL you must specify the PLL's logical channel number. When reconfiguring the reference clock for the CDR you must specify the channel's logical channel number.

7’h42 [9] R control and status

When asserted, indicates an error. This bit is asserted if any of the following conditions occur:

  • The channel address is invalid.
  • The PHY address is invalid.
  • The address offset is invalid.
[8] R MIF Busy. When asserted, indicates that a reconfiguration operation is in progress.
[1] W Read. Writing a 1 to this bit triggers a read operation.
[0] W Write. Writing a 1 to this bit triggers a write operation.
7’h43 [3:0] RW pll_offset Specifies the 4-bit register address used for indirect to the PLL registers on the reconfiguration bus. Refer to Table 16–21 for offsets and values.
7’h44 [15:0] RW data Specifies the read or write data.
Note: All undefined register bits are reserved.
Table 336.  PLL Reconfiguration Offsets and Values
Offset Bits R/W Name Description
0x0 [2:0] RW logical refclk selection

When written initiates reference clock change to the logical reference clock indexed by bits [2:0].

This index refers to the Number of input clocks on the Reconfiguration tab. You can specify up to 5 input clocks. When performing a reference clock switch for an ATX PLL you must stream in an ATX MIF.

This offset is used to switch the reference clock for CMU PLLs. To perform a reference clock switch for ATX PLLs use MIF mode 0 and stream the ATX PLL MIF.

0x1 [2:0] RW logical PLL selection

When written initiates a clock generation block (CGB) switch to logical PLL indexed by bits [2:0].

This index refers to the Number of TX PLLs selected on the Reconfiguration tab. You can specify up to 4 input clocks. If you set the Main TX PLL logical index to 0, the Intel® Quartus® Prime software initializes your design using the first PLL defined.

0x2 [24:0] RO refclk physical mapping Specifies the logical to physical refclk for current logical channel.
0x3 [14:0] RO PLL physical mapping Specifies the logical to physical clock generation block word for current logical channel.

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