17.28. Two PHY IP Core Instances Each with Non-Bonded Channels
For each transceiver PHY IP core instance, the Intel® Quartus® Prime software assigns the data channels sequentially beginning at logical address 0 and assigns the TX PLLs the subsequent logical addresses.
The following table illustrates the logical channel numbering for two transceiver PHY IP cores, one with 4 channels and one with 2 channels.
|Instance||Channel||Logical Channel Number|
|Instance 0||Channel 0||0|
|Instance 1||Channel 0||8|
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