V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

7.12.2. SDR XGMII RX Interface

This section describes the signals in the SDR RX XGMII interface.
Table 89.  SDR RX XGMII Interface
Signal Name Direction Description
xgmii_rx_dc_[71:0] Input

Contains 4 lanes of data and control for XGMII. Each lane consists of 16 bits of data and 2 bits of control.

  • Lane 0–[7:0]/[8], [43:36]/[44]
  • Lane 1–[16:9]/[17], [52:45]/[53]
  • Lane 2–[25:18]/[26], [61:54]/[62]
  • Lane 3–[34:27]/[35],[70:63]/[71]
xgmii_rx_clk Output The XGMII SDR RX clock which runs at 156.25 MHz.

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