V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

5.15. Register Interface Signals

The Avalon-MM master interface signals provide access to all registers.
Refer to the Typical Slave Read and Write Transfers and Master Transfers sections in the Avalon Memory-Mapped Interfaces chapter of the Avalon Interface Specifications for timing diagrams.
Table 59.  Avalon-MM Interface Signals
Signal Name Direction Description
mgmt_clk Input The clock signal that controls the Avalon-MM PHY management, interface. If you plan to use the same clock for the PHY management interface and transceiver reconfiguration, you must restrict the frequency range to 100-125 MHz to meet the specification for the transceiver reconfiguration clock.
mgmt_clk_reset Input Resets the PHY management interface. This signal is active high and level sensitive.
mgmt_addr[7:0] Input 8-bit Avalon-MM address.
mgmt_writedata[31:0] Input Input data.
mgmt_readdata[31:0] Output Output data.
mgmt_write Input Write signal. Active high.
mgmt_read Input Read signal. Active high.
mgmt_waitrequest Output When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request. When asserted, control signals to the Avalon-MM slave interface must remain constant.