V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

12.8. Clock Interface for Deterministic Latency PHY

This section describes the clocks for the Deterministic Latency PHY IP core.

The following table describes clocks for the Deterministic Latency PHY. The input reference clock, pll_ref_clk, drives a PLL inside the PHY-layer block, and a PLL output clock, rx_clkout is used for all data, command, and status inputs and outputs.

Table 174.  Clock Signals
Signal Name Direction Description
pll_ref_clk Input Reference clock for the PHY PLLs. Frequency range is 60-700 MHz.

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