V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

17.19. MIF Generation

The MIF stores the configuration data for the transceiver PHY IP cores. The Intel® Quartus® Prime software automatically generates MIFs after each successful compilation.

MIFs are stored in the reconfig_mif folder of the project's working directory. This folder stores all MIFs associated with the compiled project for each transceiver PHY IP core instance in the design. The parameter settings of PHY IP core instance reflect the currently specified MIF. You can store the MIF in an on-chip ROM or any other type of memory. This memory must connect to the MIF reconfiguration management interface.

The following example shows file names for the .mif files for a design with two channels. This design example includes two transceiver PHY IP core instances running at different data rates. Both transceiver PHY IP core instances have two TX PLLs specified to support both 1 Gbps and 2.5 Gbps data rates. The Intel® Quartus® Prime software generates two TX PLL .mif files for each PLL. The difference between the .mif files is the PLL reference clock specified. To dynamically reconfigure the channel from the initially specified data rate to a new data rate, you can use the MIF streaming function to load the other .mif.

Note: When reconfiguration is limited to a few settings, you can create a partial .mif that only includes the settings that must be updated. Refer to Reduced MIF Creation for more information about creating a partial .mif file.

Intel® Quartus® Prime Generated MIF Files

<project_dir>/ reconfig_mif/inst0_1g_channel.mif

<project_dir>/ reconfig_mif/inst0_1g_txpll0.mif

<project_dir>/ reconfig_mif/inst0_1g_txpll1.mif

<project_dir>/ reconfig_mif/inst0_2p5g_channel.mif

<project_dir>/ reconfig_mif/inst0_2p5g_txpll0.mif

<project_dir>/ reconfig_mif/inst0_2p5g_txpll1.mif

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