V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

4.4.3. 10GBASE-R Parameters

The 10GBASE-R parameters specify basic features of the 10GBASE-R PCS. The FEC options allow you to specify the FEC ability.
Table 27.  10GBASE-R Parameters
Parameter Name Options Description
Enable IEEE 1588 Precision Time Protocol On/Off When you turn this option On, the core includes logic to implement the IEEE 1588 Precision Time Protocol.
Reference clock frequency 644.53125MHz

322.265625MHz

Specifies the input reference clock frequency. The default is 322.265625MHz.
PLL Type ATX

CMU

Specifies the PLL type. You can specify either a CMU or ATX PLL. The ATX PLL has better jitter performance at higher data rates than the CMU PLL. Another advantage of the ATX PLL is that it does not use a transceiver channel, while the CMU PLL does.
Enable additional control and status pins On/Off When you turn this option On, the core includes the rx_block_lock and rx_hi_ber ports.
Enable rx_recovered_clk pin On/Off When you turn this option On, the core includes the rx_recovered_clk port.
Enable pll_locked status port On/Off When you turn this option On, the core includes the pll_locked port.
Table 28.  FEC Options
Parameter Name Options Description
Include FEC sublayer On/Off When you turn this option On, the core includes logic to implement FEC and a soft 10GBASE-R PCS.
Set FEC_ability bit on power up and reset On/Off When you turn this option On, the core sets the FEC ability bit on power up and reset.
Set FEC_Enable bit on power up and reset On/Off When you turn this option On, the core sets the FEC enable bit on power up and reset.
Set FEC_Error_Indication_ability bit on power up and reset On/Off When you turn this option On, the core indicates errors to the PCS.
Good parity counter threshold to achieve FEC block lock Default value: 4 Specifies the number of good parity blocks the RX FEC module must receive before indicating block lock as per Clause 74.10.2.1 of IEEE 802.3ap-2007.
Invalid parity counter threshold to lose FEC block lock Default value: 8 Specifies the number of bad parity blocks the RX FEC module must receive before indicating loss of block lock as per Clause 74.10.2.1 of IEEE 802.3ap-2007.
Use M20K for FEC Buffer (if available) On/Off When you turn this option On, the Intel® Quartus® Prime software saves resources by replacing the FEC buffer with M20K memory.

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