12.6. Interfaces for Deterministic Latency PHY
This section describes the top-level signals of the Deterministic Latency PHY IP Core.
The following figure illustrates the top-level signals of the Deterministic Latency PHY IP Core. The variables in the figure represent the following parameters:
- <n>—The number of lanes
- <w>—The width of the FPGA fabric to transceiver interface per lane
- <s>— The symbol size
- <p>—The number of PLLs
The block diagram shown in the MegaWizard Plug-In Manager labels the external pins with the interface type and places the interface name inside the box. The interface type and name are used in the _hw.tcl file that describes the component. If you turn on Show signals, the block diagram displays all top-level signal names.