12.13. Channel Placement and Utilization for Deterministic Latency PHY
This section describes the channel placement utilization restrictions for the Deterministic Latency PHY IP core.
The Deterministic Latency PHY IP Core has the following restriction on channel placement:
- Channels 1 and 2 in transceiver banks GXB_L0 and GXB_R0 of Arria V devices are not available for deterministic latency protocols. However, in Arria V GZ devices, these channels are available for deterministic latency protocols.
The following figure shows the placement of transceiver banks in Arria V devices and indicates the channels that are not available.
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