V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

7.18. XAUI PHY Dynamic Reconfiguration for Arria V, Arria V GZ, Cyclone V and Stratix V Devices

The Arria V, Arria V GZ, Cyclone V, and Stratix V devices use the Transceiver Reconfiguration Controller IP Core for dynamic reconfiguration.

For more information about this IP core, refer to Chapter 16, Transceiver Reconfiguration Controller IP Core.

Each channel and each TX PLL have separate dynamic reconfiguration interfaces. The MegaWizard Plug-In Manager provides informational messages on the connectivity of these interfaces.

Informational Messages for the Transceiver Reconfiguration Interface

PHY IP will require 8 reconfiguration interfaces for connection to the external reconfiguration controller.Reconfiguration interface offsets 0-3 are connected to the transceiver channels.Reconfiguration interface offsets 4-7 are connected to the transmit PLLs.

Although you must initially create a separate reconfiguration interface for each channel and TX PLL in your design, when the Intel® Quartus® Prime software compiles your design, it reduces the number of reconfiguration interfaces by merging reconfiguration interfaces. The synthesized design typically includes a reconfiguration interface for at least three channels because three channels share an Avalon-MM slave interface which connects to the Transceiver Reconfiguration Controller IP Core. Conversely, you cannot connect the three channels that share an Avalon-MM interface to different Transceiver Reconfiguration Controller IP Cores. Doing so causes a Fitter error. For more information, refer to “Transceiver Reconfiguration Controller to PHY IP Connectivity”.

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