V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

7.3. XAUI PHY Performance and Resource Utilization for Stratix IV Devices

This section describes performance and resource utilization for Stratix IV Devices

The following table shows the typical expected device resource utilization for different configurations using the current version of the Intel® Quartus® Prime software targeting a Stratix IV GX (EP4SG230KF40C2ES) device. The numbers of combinational ALUTs, logic registers, and memory bits are rounded to the nearest 100.

Table 85.  XAUI PHY Performance and Resource Utilization—Stratix IV GX Device
Implementation Number of 3.125 Gbps Channels Combinational ALUTS Dedicated Logic Registers Memory Bits
Soft XAUI 4 4500 3200 5100
Hard XAUI 4 2000 1300 0

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