7.17. XAUI PHY Dynamic Reconfiguration for Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX
For more information about the ALTGX_RECONFIG Megafunction, refer to ALTGX_RECONFIG Megafunction User Guide for Stratix IV Devices in volume 2 of the Stratix IV Device Handbook.
If your XAUI PHY IP Core includes a single transceiver quad, these signals are internal to the core. If your design uses more than one quad, the reconfiguration signals are external.
|reconfig_to_xcvr[3:0]||Input||Reconfiguration signals from the Transceiver Reconfiguration IP Core to the XAUI transceiver.|
|reconfig_from_xcvr[<n>:0]||Output||Reconfiguration signals from the XAUI transceiver to the Transceiver Reconfiguration IP Core. The size of this bus is depends on the device. For the soft PCS in Stratix IV GX and GT devices, < n > = 68 bits. For hard XAUI variants, < n > = 16. For Stratix V devices, the number of bits depends on the number of channels specified. Refer to Chapter 16, Transceiver Reconfiguration Controller IP Core for more information.|
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