10.4.8. Dynamic Reconfiguration
Each channel and each TX PLL have separate dynamic reconfiguration interfaces. The MegaWizard Plug-In Manager provides informational messages on the connectivity of these interfaces. The following example shows the messages for a single duplex channel parameterized for the 1.25 GIGE protocol.
Although you must initially create a separate reconfiguration interface for each channel and TX PLL in your design, when the Intel® Quartus® Prime software compiles your design, it reduces the number of reconfiguration interfaces by merging reconfiguration interfaces. The synthesized design typically includes a reconfiguration interface for at least three channels because three channels share an Avalon-MM slave interface which connects to the Transceiver Reconfiguration Controller IP Core. Conversely, you cannot connect the three channels that share an Avalon-MM interface to different Transceiver Reconfiguration Controller IP Cores. Doing so causes a Fitter error.
Informational Messages for the Transceiver Reconfiguration Interface
PHY IP will require 2 reconfiguration interfaces for connection to the external reconfiguration controller. Reconfiguration interface offset 0 is connected to the transceiver channel. Reconfiguration interface offset 1 is connected to the transmit PLL.
|reconfig_to_xcvr [( <n> 70-1):0]||Input||Reconfiguration signals from the Transceiver Reconfiguration Controller. <n> grows linearly with the number of reconfiguration interfaces.|
|reconfig_from_xcvr [( <n> 46-1):0]||Output||Reconfiguration signals to the Transceiver Reconfiguration Controller. <n> grows linearly with the number of reconfiguration interfaces.|
Overriding Logical Channel 0 Channel Assignment Restrictions in Stratix V Devices for ×6 or ×N Bonding
set_parameter -name pma_bonding_master "\"1\"" -to "<custom phy instance>|altera_xcvr_custom:my_custom_phy_inst| sv_xcvr_custom_nr:S5|sv_xcvr_custom_native:transceiver_core| sv_xcvr_native:gen.sv_xcvr_native_insts.gen_bonded_group.sv_xcvr_native_inst"
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