5.23. 1G/10GbE PHY State Machine Logic Requirements
The state machine should implement the following logic. You can modify this logic based on your system requirements:
- Wait for reconfig_busy from the Transceiver Reconfiguration Controller to be deasserted and the tx_ready and rx_ready signals from the Transceiver PHY Reset Controller to be asserted. These conditions indicate that the system is ready to service a reconfiguration request.
- Set the appropriate channel for reconfiguration.
- Initiate the MIF streaming process. The state machine should also select the appropriate MIF (stored in the ROMs) to stream based on the requested mode.
- Wait for the reconfig_busy signal from the Transceiver Reconfiguration Controller to assert and then deassert indicating the reconfiguration process is complete.
- Toggle the digital resets for the reconfigured channel and wait for the link to be ready.
- Deassert the ack/busy signal for the selected channel. Deassertion of ack/busy indicates to the arbiter that the reconfiguration process is complete and the system is ready to service another request.
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