V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

14.7.2. Standard PCS Interface Ports

This section describes the PCS interface.
Figure 76. Standard PCS Interfaces
Table 248.  Standard PCS Interface Ports 

Name

Dir

Synchronous to tx_std_coreclkin/rx_std_coreclkin

Description

Clocks
tx_std_clkout[<n>-1:0]

Output

TX Parallel clock output.

rx_std_clkout[<n>-1:0]

Output

RX parallel clock output. The CDR circuitry recovers RX parallel clock from the RX data stream.

tx_std_coreclkin[<n>-1:0]

Input

TX parallel clock input from the FPGA fabric that drives the write side of the TX phase compensation FIFO.

rx_std_coreclkin[<n>-1:0]

Input

RX parallel clock that drives the read side of the RX phase compensation FIFO.

Phase Compensation FIFO
rx_std_pcfifo_full[<n>-1:0]

Output

Yes

RX phase compensation FIFO full status flag.

rx_std_pcfifo_empty[<n>-1:0]

Output

Yes

RX phase compensation FIFO status empty flag.

tx_std_pcfifo_full[<n>-1:0]

Output

Yes

TX phase compensation FIFO status full flag.

tx_std_pcfifo_empty[<n>-1:0]

Output

Yes

TX phase compensation FIFO status empty flag.

Byte Ordering
rx_std_byteorder_ ena[<n>-1:0]

Input

No

Byte ordering enable. When this signal is asserted, the byte ordering block initiates a byte ordering operation if the Byte ordering control mode is set to manual. Once byte ordering has occurred, you must deassert and reassert this signal to perform another byte ordering operation. This signal is an synchronous input signal; however, it must be asserted for at least 1 cycle of rx_std_clkout.

rx_std_byteorder_flag[<n>-1:0]

Output

Yes

Byte ordering status flag. When asserted, indicates that the byte ordering block has performed a byte order operation. This signal is asserted on the clock cycle in which byte ordering occurred. This signal is synchronous to the rx_std_clkout clock. You must a synchronizer this signal.

Byte Serializer and Deserializer
rx_std_byterev_ena[<n>-1:0]

Input

No

This control signal is available in when the PMA width is 16 or 20 bits. When asserted, enables byte reversal on the RX interface.

8B/10B
rx_std_polinv[<n>-1:0]

Input

No

Polarity inversion for the 8B/10B decoder, When set, the RX channels invert the polarity of the received data. You can use this signal to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swapped the positive and negative signals. The polarity inversion function operates on the word aligner input.

tx_std_polinv[<n>-1:0]

Input

No

Polarity inversion, part of 8B10B encoder, When set, the TX interface inverts the polarity of the TX data.

Rate Match FIFO
rx_std_rmfifo_empty[<n>-1:0]

Output

No

Rate match FIFO empty flag. When asserted, the rate match FIFO is empty. This port is only used for XAUI, GigE, and Serial RapidIO in double width mode. In double width mode, the FPGA data width is twice the PCS data width to allow the fabric to run at half the PCS frequency

rx_std_rmfifo_ full[<n>-1:0]

Output

No

Rate match FIFO full flag. When asserted the rate match FIFO is full. You must synchronize this signal. This port is only used for XAUI, GigE, and Serial RapidIO in double width mode.

Word Aligner
rx_std_bitrev_ena [<n>-1:0]

Input

No

When asserted, enables bit reversal on the RX interface. Bit order may be reversed if external transmission circuitry transmits the most significant bit first. When enabled, the receive circuitry receives all words in the reverse order. The bit reversal circuitry operates on the output of the word aligner.

tx_std_bitslipboundary sel[5<n>-1:0]

Input

No

BitSlip boundary selection signal. Specifies the number of bits that the TX bit slipper must slip.

rx_std_bitslipboundary sel[5<n>-1:0]

Output

No

This signal operates when the word aligner is in bitslip word alignment mode. It reports the number of bits that the RX block slipped to achieve deterministic latency.

rx_std_runlength_err[<n>-1:0]

Output

No

When asserted, indicates a run length violation. Asserted if the number of consecutive 1s or 0s exceeds the number specified in the parameter editor GUI.

rx_st_wa_patternalign

Input

No

Active when you place the word aligner in manual mode. In manual mode, you align words by asserting rx_st_wa_patternalign. rx_st_wa_patternalign is edge sensitive.

For more information refer to the Word Aligner section in the Transceiver Architecture in Arria V Devices.

rx_std_wa_a1a2size [<n>-1:0]

Input

No

Used for the SONET protocol. Assert when the A1 and A2 framing bytes must be detected. A1 and A2 are SONET backplane bytes and are only used when the PMA data width is 8 bits.

rx_std_bitslip [<n>-1:0]

Input

No

Used when word aligner mode is bitslip mode. For every rising edge of the rx_std_bitslip signal, the word boundary is shifted by 1 bit. Each bitslip removes the earliest received bit from the received data. This is an asynchronous input signal and inside there is a synchronizer to synchronize it with rx_pma_clk/rx_clkout.

PRBS
rx_std_prbs_done

Output

Yes

When asserted, indicates the verifier has aligned and captured consecutive PRBS patterns and the first pass through a polynomial is complete. The generator has restarted the polynomial.

rx_std_prbs_err

Output

Yes

When asserted, indicates an error only after the rx_std_prbs_done signal has been asserted. This signal pulses for every error that occurs. Errors can only occur once per word.

To clear the PRBS pattern and deassert the rx_std_prbs_done signal by writing to the memory-mapped register PRBS Error Clear that you access through the Transceiver Reconfiguration Controller IP Core.

Miscellaneous
tx_std_elecidle [<n>-1:0]

Input

When asserted, enables a circuit to detect a downstream receiver. This signal must be driven low when not in use because it causes the TX PMA to enter electrical idle mode with the TX serial data signals in tristate mode.

rx_std_signaldetect[<n>-1:0]

Output

No

Signal threshold detect indicator. When asserted, it indicates that the signal present at the receiver input buffer is above the programmed signal detection threshold value. You must synchronize this signal.

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