V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

6.4.3. GMII Signals

The 16-bit TX and RX GMII supports 1GbE and 2.5GbE at 62.5 MHz and 156.25 MHz respectively.

Table 77.  GMII Signals
Signal Name Direction Width Description
TX GMII signals—synchronous to tx_clkout
gmii16b_tx_d

Input

16

TX data from the MAC. The MAC sends the lower byte first followed by the upper byte.

gmii16b_tx_en

Input

2

When asserted, indicates the start of a new frame from the MAC. Bit[0] corresponds to gmii16b_tx_d[7:0]; bit[1] corresponds to gmii16b_tx_d[15:8].

This signal remains asserted until the PHY receives the last byte of the data frame.

gmii16b_tx_err

Input

2

When asserted, indicates an error. Bit[0] corresponds to gmii16b_tx_err[7:0]; bit[1] corresponds to gmii16b_tx_err[15:8].

The bits can be asserted at any time during a frame transfer to indicate an error in the current frame.

gmii16b_tx_latency Output 22 The latency of the PHY excluding the PMA block on the TX datapath:
  • Bits [21:10]: The number of clock cycles.
  • Bits [9:0]: The fractional number of clock cycles.

This signal is available when only the Enable IEEE 1588 Precision Time Protocol parameter is selected.

RX GMII signals—synchronous to rx_clkout
gmii16b_rx_d

Output

16

RX data to the MAC. The PHY sends the lower byte first followed by the upper byte. Rate matching is done by the PHY on the RX data from the RX recovered clock to rx_clkout.

gmii16b_rx_err

Output

2

When asserted, indicates an error. Bit[0] corresponds to gmii16b_rx_err[7:0]; bit[1] corresponds to gmii16b_rx_err[15:8].

The bits can be asserted at any time during a frame transfer to indicate an error in the current frame.

gmii16b_rx_dv

Output

2

When asserted, indicates the start of a new frame. Bit[0] corresponds to gmii16b_rx_d[7:0]; bit[1] corresponds to gmii16b_rx_d[15:8].

This signal remains asserted until the PHY sends the last byte of the data frame.

gmii16b_rx_latency Output 22 The latency of the PHY excluding the PMA block on the RX datapath:
  • Bits [21:10]: The number of clock cycles.
  • Bits [9:0]: The fractional number of clock cycles.

This signal is available only when the Enable IEEE 1588 Precision Time Protocol parameter is selected.

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