V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

17.16. Transceiver Reconfiguration Controller DCD Calibration Registers

DCD runs automatically at power up. After power up, you can rerun DCD by writing to the DCD control register. Altera recommends that you run DCD calibration for Arria V and Cyclone V devices if the data rate is greater than 4.9152 Gbps.

Note: All undefined register bits are reserved.
Table 337.   DCD Registers
Reconfig Addr Bits R/W Register Name Description
7’h48 [9:0] RW logical channel number The logical channel number. Must be specified when performing dynamic updates. The Transceiver Reconfiguration Controller maps the logical address to the physical address.
7’h4B [6:0] RW dcd offset Specifies the offset of the DCD setting to be reconfigured. PMA Offsets and Values describes the valid offset values.
7’h4C [6:0] RW dcd_data Reconfiguration data for the PMA analog settings.
Note: All undefined register bits are reserved.
Table 338.  DCD Offsets and Values
Offset Bits R/W Register Name Description
0x0 [5:0] RW dcd_control

Writing 1'b1 to this bit to manually triggers DCD calibration.

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