V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

14.5. PMA Parameters

This section describes the options available for the PMA.

For more information about the PMA, refer to the PMA Architecture section in the Transceiver Architecture in Arria V Devices. Some parameters have ranges where the value is specified as Device Dependent. For such parameters, the possible range of frequencies and bandwidths depends on the device, speed grade, and other design characteristics. Refer to Device Datasheet for Arria V Devices for specific data for Arria V devices.

Table 227.  PMA Options  




Data rate

Device Dependent

Specifies the data rate. The maximum data rate is 12.5 Gbps.

PMA direct interface width 13

8, 10, 16, 20, 64, 80

Specifies the PMA to FPGA fabric interface width for PMA Direct mode.

TX local clock division factor

1, 2, 4, 8

Specifies the value of the divider available in the transceiver channels to divide the input clock to generate the correct frequencies for the parallel and serial clocks. This divisor divides the fast clock from the PLL in nonbonded configurations.

PLL base data rate

Device Dependent

Shows the base data rate of the clock input to the TX PLL.The PLL base data rate is computed from the TX local clock division factor multiplied by the data rate.

Select a PLL base data rate that minimizes the number of PLLs required to generate all the clocks for data transmission. By selecting an appropriate PLL base data rate, you can change data rates by changing the TX local clock division factor used by the clock generation block.

13 PMA Direct mode is supported for Arria V GT, ST, and GZ devices only.