17.4.1. General Options Parameters
Arria V GZ
|Specifies the device family. The reconfiguration functions available for Arria V and Cyclone V devices are a subset of those available for Stratix V devices. Refer to Device Support for Dynamic Reconfiguration for more information about available functions.|
|Number of reconfiguration interfaces||<IF>||
Specifies the total number of reconfiguration interfaces that connect to the Transceiver Reconfiguration Controller. There is one interface for each channel and TX PLL.
When you specify the parameters for a transceiver PHY, the message window displays the number of interfaces required.
|Optional interface grouping||
<Grp1 >,<Grp2 >,
Specifies the grouping of reconfiguration interfaces as a comma-separated list with each integer indicating the total number of reconfiguration interfaces that are connected to a transceiver PHY instance. Leave this entry blank if all reconfiguration interfaces connect to the same transceiver PHY instance.
Refer to Understanding Logical Channel Numbering for more information about grouping interfaces.
|Transceiver Calibration Functions|
|Enable offset cancellation||On||
When enabled, the Transceiver Reconfiguration Controller includes the offset cancellation functionality. This option is always on. Offset cancellation occurs automatically at power-up and runs only once.
|Enable duty cycle calibration||On/Off||For Arria V devices, when enable, DCD calibrates for duty cycle distortion caused by clock network skew. DCD calibration runs once during power up. You should enable this option for protocols running at greater than 4.9152 Gbps.|
|Enable PLL calibration||On/Off||
When enabled, an algorithm that improves the signal integrity of the PLLs is included in the Transceiver Reconfiguration Controller IP Core. This feature is only available for Stratix V devices.
|Create optional calibration status ports||On/Off||When you turn this option On, the core includes tx_cal_busy and rx_cal_busy ports. These signals are asserted when calibration is active.|
|Enable Analog controls||On/Off||When enabled, TX and RX signal conditioning features are enabled.|
|Enable EyeQ block||On/Off||When enabled, you can use the EyeQ, the on-chip signal quality monitoring circuitry, to estimate the actual eye opening at the receiver. This feature is only available for Stratix V devices.|
|Enable decision feedback equalizer (DFE) block||On/Off||When you turn this option On, the Transceiver Reconfiguration Controller includes logic to perform DFE|
|Enable adaptive equalization (AEQ) block||On/Off||When enabled, the Transceiver Reconfiguration Controller includes logic to perform AEQ. This feature is only available for Stratix V devices.|
|Enable channel/PLL reconfiguration||On/Off||When enabled, the Transceiver Reconfiguration Controller includes logic to include both channel and PLL reconfiguration.|
|Enable PLL reconfiguration support block||On/Off||When enabled, the Transceiver Reconfiguration Controller includes logic to perform PLL reconfiguration.|
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