V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

5.22. 1G/10GbE PHY Arbitration Logic Requirements

This topic describes the arbitration functionality that you must implement.

The arbiter should implement the following logic. You can modify this logic based on your system requirements:

  1. Accept requests from the sequencer (if Enable automatic speed detection is turned On in the GUI) . Prioritize requests to meet system requirements. Requests should consist of the following two buses:
    • Channel number—specifies the requested channel
    • Mode—specifies 1G or 10G mode for the corresponding channel
  2. Select a channel for reconfiguration and send an ack/busy signal to the requestor. The requestor should deassert its request signal when the ack/busy is received.
  3. Pass the selected channel and rate information to the state machine for processing.
  4. Wait for a done signal from the state machine indicating that the reconfiguration process is complete and it is ready to service another request.