V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

1.1. Protocol-Specific Transceiver PHYs

The protocol-specific transceiver PHYs configure many PCS to meet the requirements of a specific protocol, leaving fewer parameters for you to specify.

Altera offers the following protocol-specific transceiver PHYS:

  • 1G/10 Gbps Ethernet
  • 10GBASE-R
  • Backplane Ethernet 10GBASE-KR PHY
  • Interlaken
  • PHY IP Core for PCI Express (PIPE)
  • XAUI

These transceiver PHYs include an Avalon® Memory-Mapped (Avalon-MM) interface to access control and status registers and an Avalon Streaming (Avalon-ST) interface to connect to the MAC for data transfer.

The following figure illustrates the top level modules that comprise the protocol-specific transceiver PHY IP cores. As illustrated, the Altera Transceiver Reconfiguration Controller IP Core is instantiated separately.

Figure 1. Transceiver PHY Top-Level Modules

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