V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

21.3. Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices

This section lists the differences between the top-level signals in Stratix IV GX and Stratix V GX/GS devices.
Table 356.  Correspondences between XAUI PHY Stratix IV GX and Stratix V Device Signals
Stratix IV GX Devices21 Stratix V Devices
Signal Name Width Signal Name Width
Reference Clocks and Resets
pll_inclk 1 refclk 1
rx_cruclk [<n> -1:0] Not available
coreclkout 1 xgmii_rx_clk 1
rx_coreclk [<n> -1:0] Not available
tx_coreclk [<n> -1:0] xgmii_tx_clk 1
Not available rx_pma_ready 1
Not available tx_pma_ready 1
Data Ports
rx_datain [<n> -1:0] xaui_rx_serial [3:0]
tx_datain [16<n> -1:0] xgmii_tx_dc [63:0]
rx_dataout [16<n> -1:0] xgmii_rx_dc [63:0]
tx_dataout [<n> -1:0] xaui_tx_serial [3:0]
Optional TX and RX Status Ports
gxb_powerdown [<n>/4 -1:0] Not available, however you can access them through the Avalon-MM PHY management interface.
pll_locked [<n> -1:0] Not available
rx_locktorefclk [<n> -1:0] Not available
rx_locktodata [<n> -1:0] Not available
rx_pll_locked [<n>/4 -1:0] Not available
rx_freqlocked [<n>/4 -1:0] Not available
rx_phase_comp_fifo_error [<n>/4 -1:0] Not available
tx_phase_comp_fifo_error [<n>/4 -1:0] Not available
cal_blk_powerdown Not available
rx_syncstatus [2<n> -1:0] rx_syncstatus [<n> *2 -1:0]
rx_patterndetect [2<n> -1:0] Not available
rx_invpolarity [2<n> -1:0] Not available
rx_ctrldetect [2<n> -1:0] Not available
rx_errdetect [2<n> -1:0] rx_errdetect [<n> *2 -1:0]
rx_disperr [2<n> -1:0] rx_disperr [<n> *2 -1:0]
tx_invpolarity [2<n> -1:0] Not available
rx_runningdisp [2<n> -1:0] Not available
rx_rmfifofull [2<n> -1:0] Not available
rx_rmfifoempty [2<n> -1:0] Not available
rx_rmfifodatainserted [2<n> -1:0] Not available
rx_rmfifodatadeleted [2<n> -1:0] Not available
Transceiver Reconfiguration
cal_blk_clk 1 These signals are included in the reconfig_to_xcvr bus.
reconfig_clk 1
reconfig_togxb [3:0] reconfig_to_xcvr Variable
reconfig_fromgxb [16:0] reconfig_from_xcvr Variable
Avalon MM Management Interface
Not Available phy_mgmt_clk_rst 1
phy_mgmt_clk 1
phy_mgmt_address [8:0]
phy_mgmt_read 1
phy_mgmt_readdata [31:0]
phy_mgmt_write 1
phy_mgmt_writedat [31:0]
21 <n> = the number of lanes. <d> = the total deserialization factor from the pin to the FPGA fabric.