V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

17.29. Transceiver Reconfiguration Controller to PHY IP Connectivity

This section describes connecting a Transceiver Reconfiguration Controller to the transceiver channels and PLLs in your design.

You can connect a single Transceiver Reconfiguration Controller to all of the transceiver channels and PLLs in your design. You can also use multiple Transceiver Reconfiguration Controllers to facilitate placement and routing of the FPGA. However, the three, upper or lower contiguous channels in a transceiver bank must be connected to the same reconfiguration controller.

The following figure illustrates connections between the Transceiver Reconfiguration Controller and transceiver channels after Intel® Quartus® Prime compilation.

Figure 99. Correct Connections

The following figure illustrates incorrect connections between two Transceiver Reconfiguration Controllers and six transceiver channels. Two Transceiver Reconfiguration Controllers cannot access a single reconfiguration interface because there is no arbitration logic to prevent concurrent access. The configuration shown results in a Intel® Quartus® Prime compilation error.

Figure 100. Incorrect Connections

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