V-Series Transceiver PHY IP Core User Guide

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ID 683171
Date 7/26/2022
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to the Protocol-Specific and Native Transceiver PHYs 2. Getting Started Overview 3. 10GBASE-R PHY IP Core 4. Backplane Ethernet 10GBASE-KR PHY IP Core 5. 1G/10Gbps Ethernet PHY IP Core 6. 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core 7. XAUI PHY IP Core 8. Interlaken PHY IP Core 9. PHY IP Core for PCI Express (PIPE) 10. Custom PHY IP Core 11. Low Latency PHY IP Core 12. Deterministic Latency PHY IP Core 13. Stratix V Transceiver Native PHY IP Core 14. Arria V Transceiver Native PHY IP Core 15. Arria V GZ Transceiver Native PHY IP Core 16. Cyclone V Transceiver Native PHY IP Core Overview 17. Transceiver Reconfiguration Controller IP Core Overview 18. Transceiver PHY Reset Controller IP Core 19. Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices 20. Analog Parameters Set Using QSF Assignments 21. Migrating from Stratix IV to Stratix V Devices Overview 22. Additional Information for the Transceiver PHY IP Core
1. Introduction to the Protocol-Specific and Native Transceiver PHYs x
1.1. Protocol-Specific Transceiver PHYs 1.2. Native Transceiver PHYs 1.3. Non-Protocol-Specific Transceiver PHYs 1.4. Transceiver PHY Modules 1.5. Transceiver Reconfiguration Controller 1.6. Resetting the Transceiver PHY 1.7. Running a Simulation Testbench 1.8. Unsupported Features
2. Getting Started Overview x
2.1. Installation and Licensing of IP Cores 2.2. Design Flows 2.3. MegaWizard Plug-In Manager Flow
2.3. MegaWizard Plug-In Manager Flow x
2.3.1. Specifying Parameters 2.3.2. Simulate the IP Core
3. 10GBASE-R PHY IP Core x
3.1. 10GBASE-R PHY Release Information 3.2. 10GBASE-R PHY Device Family Support 3.3. 10GBASE-R PHY Performance and Resource Utilization for Stratix IV Devices 3.4. 10GBASE-R PHY Performance and Resource Utilization for Arria V GT Devices 3.5. 10GBASE-R PHY Performance and Resource Utilization for Arria V GZ and Stratix V Devices 3.6. Parameterizing the 10GBASE-R PHY 3.7. General Option Parameters 3.8. Analog Parameters for Stratix IV Devices 3.9. 10GBASE-R PHY Interfaces 3.10. 10GBASE-R PHY Data Interfaces 3.11. 10GBASE-R PHY Status, 1588, and PLL Reference Clock Interfaces 3.12. Optional Reset Control and Status Interface 3.13. 10GBASE-R PHY Clocks for Arria V GT Devices 3.14. 10GBASE-R PHY Clocks for Arria V GZ Devices 3.15. 10GBASE-R PHY Clocks for Stratix IV Devices 3.16. 10GBASE-R PHY Clocks for Stratix V Devices 3.17. 10GBASE-R PHY Register Interface and Register Descriptions 3.18. 10GBASE-R PHY Dynamic Reconfiguration for Stratix IV Devices 3.19. 10GBASE-R PHY Dynamic Reconfiguration for Arria V and Stratix V Devices 3.20. 1588 Delay Requirements 3.21. 10GBASE-R PHY TimeQuest Timing Constraints 3.22. 10GBASE-R PHY Simulation Files and Example Testbench
4. Backplane Ethernet 10GBASE-KR PHY IP Core x
4.1. 10GBASE-KR PHY Release Information 4.2. Device Family Support 4.3. 10GBASE-KR PHY Performance and Resource Utilization 4.4. Parameterizing the 10GBASE-KR PHY 4.5. 10GBASE-KR PHY IP Core Functional Description 4.6. 10GBASE-KR Dynamic Reconfiguration from 1G to 10GbE 4.7. 10GBASE-KR PHY Arbitration Logic Requirements 4.8. 10GBASE-KR PHY State Machine Logic Requirements 4.9. Forward Error Correction (Clause 74) 4.10. 10BASE-KR PHY Interfaces 4.11. 10GBASE-KR PHY Clock and Reset Interfaces 4.12. Register Interface Signals 4.13. 10GBASE-KR PHY Register Definitions 4.14. PMA Registers 4.15. PCS Registers 4.16. Creating a 10GBASE-KR Design 4.17. Editing a 10GBASE-KR MIF File 4.18. Design Example 4.19. SDC Timing Constraints 4.20. Acronyms
4.4. Parameterizing the 10GBASE-KR PHY x
4.4.1. 10GBASE-KR Link Training Parameters 4.4.2. 10GBASE-KR Auto-Negotiation and Link Training Parameters 4.4.3. 10GBASE-R Parameters 4.4.4. 1GbE Parameters 4.4.5. Speed Detection Parameters 4.4.6. PHY Analog Parameters
4.11. 10GBASE-KR PHY Clock and Reset Interfaces x
4.11.1. 10GBASE-KR PHY Data Interfaces 4.11.2. 10GBASE-KR PHY Control and Status Interfaces 4.11.3. Daisy-Chain Interface Signals 4.11.4. Embedded Processor Interface Signals 4.11.5. Dynamic Reconfiguration Interface Signals
4.11.1. 10GBASE-KR PHY Data Interfaces x
4.11.1.1. 10GBASE-KR PHY XGMII Mapping to Standard SDR XGMII Data 4.11.1.2. 10GBASE-KR PHY Serial Data Interface 4.11.1.3. MII Interface Signals
5. 1G/10Gbps Ethernet PHY IP Core x
5.1. 1G/10GbE PHY Release Information 5.2. Device Family Support 5.3. 1G/10GbE PHY Performance and Resource Utilization 5.4. Parameterizing the 1G/10GbE PHY 5.5. 1GbE Parameters 5.6. Speed Detection Parameters 5.7. PHY Analog Parameters 5.8. 1G/10GbE PHY Interfaces 5.9. 1G/10GbE PHY Clock and Reset Interfaces 5.10. 1G/10GbE PHY Data Interfaces 5.11. XGMII Mapping to Standard SDR XGMII Data 5.12. MII Interface Signals 5.13. Serial Data Interface 5.14. 1G/10GbE Control and Status Interfaces 5.15. Register Interface Signals 5.16. 1G/10GbE PHY Register Definitions 5.17. PMA Registers 5.18. PCS Registers 5.19. 1G/10GbE GMII PCS Registers 5.20. GIGE PMA Registers 5.21. 1G/10GbE Dynamic Reconfiguration from 1G to 10GbE 5.22. 1G/10GbE PHY Arbitration Logic Requirements 5.23. 1G/10GbE PHY State Machine Logic Requirements 5.24. Editing a 1G/10GbE MIF File 5.25. Creating a 1G/10GbE Design 5.26. Dynamic Reconfiguration Interface Signals 5.27. Design Example 5.28. Simulation Support 5.29. TimeQuest Timing Constraints 5.30. Acronyms
6. 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core x
6.1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 6.2. Using the IP Core 6.3. Configuration Registers 6.4. Interface Signals
6.1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
6.1.1. Features 6.1.2. Release Information 6.1.3. Device Family Support 6.1.4. Resource Utilization
6.2. Using the IP Core x
6.2.1. Parameter Settings 6.2.2. Timing Constraints 6.2.3. Changing the PHY's Speed
6.3. Configuration Registers x
6.3.1. Register Map 6.3.2. Configuration Registers
6.4. Interface Signals x
6.4.1. Clock and Reset Signals 6.4.2. Operating Mode and Speed Signals 6.4.3. GMII Signals 6.4.4. XGMII Signals 6.4.5. Status Signals 6.4.6. Serial Interface Signals 6.4.7. Transceiver Status and Reconfiguration Signals 6.4.8. Avalon® Memory-Mapped Interface Signals
7. XAUI PHY IP Core x
7.1. XAUI PHY Release Information 7.2. XAUI PHY Device Family Support 7.3. XAUI PHY Performance and Resource Utilization for Stratix IV Devices 7.4. XAUI PHY Performance and Resource Utilization for Arria V GZ and Stratix V Devices 7.5. Parameterizing the XAUI PHY 7.6. XAUI PHY General Parameters 7.7. XAUI PHY Analog Parameters 7.8. XAUI PHY Analog Parameters for Arria II GX, Cyclone IV GX, HardCopy IV and Stratix IV Devices 7.9. Advanced Options Parameters 7.10. XAUI PHY Configurations 7.11. XAUI PHY Ports 7.12. XAUI PHY Data Interfaces 7.13. XAUI PHY Clocks, Reset, and Powerdown Interfaces 7.14. XAUI PHY PMA Channel Controller Interface 7.15. XAUI PHY Optional PMA Control and Status Interface 7.16. XAUI PHY Register Interface and Register Descriptions 7.17. XAUI PHY Dynamic Reconfiguration for Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX 7.18. XAUI PHY Dynamic Reconfiguration for Arria V, Arria V GZ, Cyclone V and Stratix V Devices 7.19. SDC Timing Constraints 7.20. Simulation Files and Example Testbench
7.12. XAUI PHY Data Interfaces x
7.12.1. SDR XGMII TX Interface 7.12.2. SDR XGMII RX Interface 7.12.3. Transceiver Serial Data Interface
7.18. XAUI PHY Dynamic Reconfiguration for Arria V, Arria V GZ, Cyclone V and Stratix V Devices x
7.18.1. Logical Lane Assignment Restriction 7.18.2. XAUI PHY Dynamic Reconfiguration Interface Signals
8. Interlaken PHY IP Core x
8.1. Interlaken PHY Device Family Support 8.2. Parameterizing the Interlaken PHY 8.3. Interlaken PHY General Parameters 8.4. Interlaken PHY Optional Port Parameters 8.5. Interlaken PHY Analog Parameters 8.6. Interlaken PHY Interfaces 8.7. Interlaken PHY Avalon-ST TX Interface 8.8. Interlaken PHY Avalon-ST RX Interface 8.9. Interlaken PHY TX and RX Serial Interface 8.10. Interlaken PHY PLL Interface 8.11. Interlaken Optional Clocks for Deskew 8.12. Interlaken PHY Register Interface and Register Descriptions 8.13. Why Transceiver Dynamic Reconfiguration 8.14. Dynamic Transceiver Reconfiguration Interface 8.15. Interlaken PHY TimeQuest Timing Constraints 8.16. Interlaken PHY Simulation Files and Example Testbench
9. PHY IP Core for PCI Express (PIPE) x
9.1. PHY for PCIe (PIPE) Device Family Support 9.2. PHY for PCIe (PIPE) Resource Utilization 9.3. Parameterizing the PHY IP Core for PCI Express (PIPE) 9.4. PHY for PCIe (PIPE) General Options Parameters 9.5. PHY for PCIe (PIPE) Interfaces 9.6. PHY for PCIe (PIPE) Input Data from the PHY MAC 9.7. PHY for PCIe (PIPE) Output Data to the PHY MAC 9.8. PHY for PCIe (PIPE) Clocks 9.9. PHY for PCIe (PIPE) Clock SDC Timing Constraints for Gen3 Designs 9.10. PHY for PCIe (PIPE) Optional Status Interface 9.11. PHY for PCIe (PIPE) Serial Data Interface 9.12. PHY for PCIe (PIPE) Register Interface and Register Descriptions 9.13. PHY for PCIe (PIPE) Link Equalization for Gen3 Data Rate 9.14. Enabling Dynamic PMA Tuning for PCIe Gen3 9.15. PHY for PCIe (PIPE) Dynamic Reconfiguration 9.16. PHY for PCIe (PIPE) Simulation Files and Example Testbench
9.13. PHY for PCIe (PIPE) Link Equalization for Gen3 Data Rate x
9.13.1. Phase 0 9.13.2. Phase 1 9.13.3. Phase 2 (Optional) 9.13.4. Phase 3 (Optional) 9.13.5. Recommendations for Tuning Link Partner’s Transmitter
9.15. PHY for PCIe (PIPE) Dynamic Reconfiguration x
9.15.1. Logical Lane Assignment Restriction
10. Custom PHY IP Core x
10.1. Device Family Support 10.2. Performance and Resource Utilization 10.3. Parameterizing the Custom PHY 10.4. Interfaces
10.3. Parameterizing the Custom PHY x
10.3.1. General Options Parameters 10.3.2. Word Alignment Parameters 10.3.3. Rate Match FIFO Parameters 10.3.4. 8B/10B Encoder and Decoder Parameters 10.3.5. Byte Order Parameters 10.3.6. PLL Reconfiguration Parameters 10.3.7. Analog Parameters 10.3.8. Presets for Ethernet
10.4. Interfaces x
10.4.1. Data Interfaces 10.4.2. Clock Interface 10.4.3. Optional Status Interface 10.4.4. Optional Reset Control and Status Interface 10.4.5. Register Interface and Register Descriptions 10.4.6. Custom PHY IP Core Registers 10.4.7. SDC Timing Constraints 10.4.8. Dynamic Reconfiguration
10.4.6. Custom PHY IP Core Registers x
10.4.6.1. PMA Common Control and Status Registers 10.4.6.2. Reset Control Registers–Automatic Reset Controller 10.4.6.3. Reset Controls –Manual Mode 10.4.6.4. PMA Control and Status Registers 10.4.6.5. Custom PCS
11. Low Latency PHY IP Core x
11.1. Device Family Support 11.2. Performance and Resource Utilization 11.3. Parameterizing the Low Latency PHY 11.4. General Options Parameters 11.5. Additional Options Parameters 11.6. PLL Reconfiguration Parameters 11.7. Low Latency PHY Analog Parameters 11.8. Low Latency PHY Interfaces 11.9. Low Latency PHY Data Interfaces 11.10. Optional Status Interface 11.11. Low Latency PHY Clock Interface 11.12. Optional Reset Control and Status Interface 11.13. Register Interface and Register Descriptions 11.14. Dynamic Reconfiguration 11.15. SDC Timing Constraints 11.16. Simulation Files and Example Testbench
12. Deterministic Latency PHY IP Core x
12.1. Deterministic Latency Auto-Negotiation 12.2. Achieving Deterministic Latency 12.3. Deterministic Latency PHY Delay Estimation Logic 12.4. Deterministic Latency PHY Device Family Support 12.5. Parameterizing the Deterministic Latency PHY 12.6. Interfaces for Deterministic Latency PHY 12.7. Data Interfaces for Deterministic Latency PHY 12.8. Clock Interface for Deterministic Latency PHY 12.9. Optional TX and RX Status Interface for Deterministic Latency PHY 12.10. Optional Reset Control and Status Interfaces for Deterministic Latency PHY 12.11. Register Interface and Descriptions for Deterministic Latency PHY 12.12. Dynamic Reconfiguration for Deterministic Latency PHY 12.13. Channel Placement and Utilization for Deterministic Latency PHY 12.14. SDC Timing Constraints 12.15. Simulation Files and Example Testbench for Deterministic Latency PHY
12.5. Parameterizing the Deterministic Latency PHY x
12.5.1. General Options Parameters for Deterministic Latency PHY 12.5.2. Additional Options Parameters for Deterministic Latency PHY 12.5.3. PLL Reconfiguration Parameters for Deterministic Latency PHY 12.5.4. Deterministic Latency PHY Analog Parameters
13. Stratix V Transceiver Native PHY IP Core x
13.1. Device Family Support for Stratix V Native PHY 13.2. Performance and Resource Utilization for Stratix V Native PHY 13.3. Parameter Presets 13.4. Parameterizing the Stratix V Native PHY 13.5. Interfaces for Stratix V Native PHY 13.6. ×6/×N Bonded Clocking 13.7. xN Non-Bonded Clocking 13.8. SDC Timing Constraints of Stratix V Native PHY 13.9. Dynamic Reconfiguration for Stratix V Native PHY 13.10. Simulation Support 13.11. Slew Rate Settings
13.4. Parameterizing the Stratix V Native PHY x
13.4.1. General Parameters for Stratix V Native PHY 13.4.2. PMA Parameters for Stratix V Native PHY 13.4.3. Standard PCS Parameters for the Native PHY 13.4.4. 10G PCS Parameters for Stratix V Native PHY
13.4.3. Standard PCS Parameters for the Native PHY x
13.4.3.1. Standard PCS Pattern Generators
13.4.4. 10G PCS Parameters for Stratix V Native PHY x
13.4.4.1. 10G PCS Pattern Generators
13.5. Interfaces for Stratix V Native PHY x
13.5.1. Common Interface Ports for Stratix V Native PHY 13.5.2. Standard PCS Interface Ports 13.5.3. 10G PCS Interface
14. Arria V Transceiver Native PHY IP Core x
14.1. Device Family Support 14.2. Performance and Resource Utilization 14.3. Parameterizing the Arria V Native PHY 14.4. General Parameters 14.5. PMA Parameters 14.6. Standard PCS Parameters 14.7. Interfaces 14.8. SDC Timing Constraints 14.9. Dynamic Reconfiguration 14.10. Simulation Support 14.11. Slew Rate Settings
14.5. PMA Parameters x
14.5.1. TX PMA Parameters 14.5.2. TX PLL Parameters 14.5.3. RX PMA Parameters
14.6. Standard PCS Parameters x
14.6.1. Phase Compensation FIFO 14.6.2. Byte Ordering Block Parameters 14.6.3. Byte Serializer and Deserializer 14.6.4. 8B/10B 14.6.5. Rate Match FIFO 14.6.6. Word Aligner and BitSlip Parameters 14.6.7. Bit Reversal and Polarity Inversion
14.7. Interfaces x
14.7.1. Common Interface Ports 14.7.2. Standard PCS Interface Ports
15. Arria V GZ Transceiver Native PHY IP Core x
15.1. Device Family Support for Arria V GZ Native PHY 15.2. Performance and Resource Utilization for Arria V GZ Native PHY 15.3. Parameter Presets 15.4. Parameterizing the Arria V GZ Native PHY 15.5. Interfaces for Arria V GZ Native PHY 15.6. SDC Timing Constraints of Arria V GZ Native PHY 15.7. Dynamic Reconfiguration for Arria V GZ Native PHY 15.8. Simulation Support 15.9. Slew Rate Settings
15.4. Parameterizing the Arria V GZ Native PHY x
15.4.1. General Parameters for Arria V GZ Native PHY 15.4.2. PMA Parameters for Arria V GZ Native PHY 15.4.3. Standard PCS Parameters for the Native PHY 15.4.4. 10G PCS Parameters for Arria V GZ Native PHY
15.4.3. Standard PCS Parameters for the Native PHY x
15.4.3.1. Standard PCS Pattern Generators
15.4.4. 10G PCS Parameters for Arria V GZ Native PHY x
15.4.4.1. 10G PCS Pattern Generators
15.5. Interfaces for Arria V GZ Native PHY x
15.5.1. Common Interface Ports for Arria V GZ Native PHY 15.5.2. Standard PCS Interface Ports 15.5.3. 10G PCS Interface
16. Cyclone V Transceiver Native PHY IP Core Overview x
16.1. Cyclone Device Family Support 16.2. Cyclone V Native PHY Performance and Resource Utilization 16.3. Parameterizing the Cyclone V Native PHY 16.4. General Parameters 16.5. PMA Parameters 16.6. Standard PCS Parameters 16.7. Interfaces 16.8. SDC Timing Constraints 16.9. Dynamic Reconfiguration 16.10. Simulation Support 16.11. Slew Rate Settings
16.5. PMA Parameters x
16.5.1. TX PMA Parameters 16.5.2. TX PLL Parameters 16.5.3. RX PMA Parameters
16.6. Standard PCS Parameters x
16.6.1. Phase Compensation FIFO 16.6.2. Byte Ordering Block Parameters 16.6.3. Byte Serializer and Deserializer 16.6.4. 8B/10B 16.6.5. Rate Match FIFO 16.6.6. Word Aligner and BitSlip Parameters 16.6.7. Bit Reversal and Polarity Inversion
16.7. Interfaces x
16.7.1. Common Interface Ports 16.7.2. Cyclone V Standard PCS Interface Ports
17. Transceiver Reconfiguration Controller IP Core Overview x
17.1. Transceiver Reconfiguration Controller System Overview 17.2. Transceiver Reconfiguration Controller Performance and Resource Utilization 17.3. Parameterizing the Transceiver Reconfiguration Controller IP Core 17.4. Parameterizing the Transceiver Reconfiguration Controller IP Core in Qsys 17.5. Transceiver Reconfiguration Controller Interfaces 17.6. Transceiver Reconfiguration Controller Memory Map 17.7. Transceiver Reconfiguration Controller Calibration Functions 17.8. Transceiver Reconfiguration Controller PMA Analog Control Registers 17.9. Transceiver Reconfiguration Controller EyeQ Registers 17.10. Transceiver Reconfiguration Controller DFE Registers 17.11. Controlling DFE Using Register-Based Reconfiguration 17.12. Transceiver Reconfiguration Controller AEQ Registers 17.13. Transceiver Reconfiguration Controller ATX PLL Calibration Registers 17.14. Transceiver Reconfiguration Controller PLL Reconfiguration 17.15. Transceiver Reconfiguration Controller PLL Reconfiguration Registers 17.16. Transceiver Reconfiguration Controller DCD Calibration Registers 17.17. Transceiver Reconfiguration Controller Channel and PLL Reconfiguration 17.18. Transceiver Reconfiguration Controller Streamer Module Registers 17.19. MIF Generation 17.20. Creating MIFs for Designs that Include Bonded or GT Channels 17.21. MIF Format 17.22. xcvr_diffmifgen Utility 17.23. Reduced MIF Creation 17.24. Changing Transceiver Settings Using Register-Based Reconfiguration 17.25. Changing Transceiver Settings Using Streamer-Based Reconfiguration 17.26. Pattern Generators for the Stratix V and Arria V GZ Native PHYs 17.27. Understanding Logical Channel Numbering 17.28. Two PHY IP Core Instances Each with Non-Bonded Channels 17.29. Transceiver Reconfiguration Controller to PHY IP Connectivity 17.30. Merging TX PLLs In Multiple Transceiver PHY Instances 17.31. Sharing Reconfiguration Interface for Multi-Channel Transceiver Designs 17.32. Loopback Modes
17.4. Parameterizing the Transceiver Reconfiguration Controller IP Core in Qsys x
17.4.1. General Options Parameters
17.5. Transceiver Reconfiguration Controller Interfaces x
17.5.1. MIF Reconfiguration Management Avalon-MM Master Interface 17.5.2. Transceiver Reconfiguration Interface 17.5.3. Reconfiguration Management Interface
17.7. Transceiver Reconfiguration Controller Calibration Functions x
17.7.1. Offset Cancellation 17.7.2. Duty Cycle Calibration 17.7.3. Auxiliary Transmit (ATX) PLL Calibration
17.9. Transceiver Reconfiguration Controller EyeQ Registers x
17.9.1. EyeQ Usage Example
17.11. Controlling DFE Using Register-Based Reconfiguration x
17.11.1. Turning on DFE Continuous Adaptive mode 17.11.2. Turning on Triggered DFE Mode 17.11.3. Setting the First Tap Value Using DFE in Manual Mode
17.17. Transceiver Reconfiguration Controller Channel and PLL Reconfiguration x
17.17.1. Channel Reconfiguration 17.17.2. PLL Reconfiguration
17.18. Transceiver Reconfiguration Controller Streamer Module Registers x
17.18.1. Mode 0 Streaming a MIF for Reconfiguration 17.18.2. Mode 1 Avalon-MM Direct Writes for Reconfiguration
17.24. Changing Transceiver Settings Using Register-Based Reconfiguration x
17.24.1. Register-Based Write 17.24.2. Register-Based Read
17.25. Changing Transceiver Settings Using Streamer-Based Reconfiguration x
17.25.1. Direct Write Reconfiguration 17.25.2. Streamer-Based Reconfiguration
17.26. Pattern Generators for the Stratix V and Arria V GZ Native PHYs x
17.26.1. Enabling the Standard PCS PRBS Verifier Using Streamer-Based Reconfiguration 17.26.2. Enabling the Standard PCS PRBS Generator Using Streamer-Based Reconfiguration 17.26.3. Enabling the 10G PCS PRBS Generator or Verifier Using Streamer-Based Reconfiguration 17.26.4. Disabling the Standard PCS PRBS Generator and Verifier Using Streamer-Based Reconfiguration
17.27. Understanding Logical Channel Numbering x
17.27.1. Two PHY IP Core Instances Each with Four Bonded Channels 17.27.2. One PHY IP Core Instance with Eight Bonded Channels
18. Transceiver PHY Reset Controller IP Core x
18.1. Device Family Support for Transceiver PHY Reset Controller 18.2. Performance and Resource Utilization for Transceiver PHY Reset Controller 18.3. Parameterizing the Transceiver PHY Reset Controller IP 18.4. Transceiver PHY Reset Controller Parameters 18.5. Transceiver PHY Reset Controller Interfaces 18.6. Timing Constraints for Bonded PCS and PMA Channels
19. Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices x
19.1. Parameterizing the Transceiver PLL PHY 19.2. Transceiver PLL Parameters 19.3. Transceiver PLL Signals
20. Analog Parameters Set Using QSF Assignments x
20.1. Making QSF Assignments Using the Assignment Editor 20.2. Analog Settings for Arria V Devices 20.3. Analog Settings for Arria V GZ Devices 20.4. Analog Settings for Cyclone V Devices 20.5. Analog Settings for Stratix V Devices
20.2. Analog Settings for Arria V Devices x
20.2.1. Analog Settings for Arria V Devices 20.2.2. Analog Settings Having Global or Computed Values for Arria V Devices
20.2.1. Analog Settings for Arria V Devices x
20.2.1.1. XCVR_IO_PIN_TERMINATION 20.2.1.2. XCVR_REFCLK_PIN_TERMINATION 20.2.1.3. XCVR_TX_SLEW_RATE_CTRL 20.2.1.4. XCVR_VCCR_ VCCT_VOLTAGE
20.2.2. Analog Settings Having Global or Computed Values for Arria V Devices x
20.2.2.1. CDR_BANDWIDTH_PRESET 20.2.2.2. PLL_BANDWIDTH_PRESET 20.2.2.3. XCVR_RX_DC_GAIN 20.2.2.4. XCVR_ANALOG_SETTINGS_PROTOCOL 20.2.2.5. XCVR_RX_COMMON_MODE_VOLTAGE 20.2.2.6. XCVR_RX_LINEAR_EQUALIZER_CONTROL 20.2.2.7. XCVR_RX_SD_ENABLE 20.2.2.8. XCVR_RX_SD_OFF 20.2.2.9. XCVR_RX_SD_ON 20.2.2.10. XCVR_RX_SD_THRESHOLD 20.2.2.11. XCVR_TX_COMMON_MODE_VOLTAGE 20.2.2.12. XCVR_TX_PRE_EMP_1ST_POST_TAP 20.2.2.13. XCVR_TX_RX_DET_ENABLE 20.2.2.14. XCVR_TX_RX_DET_MODE 20.2.2.15. XCVR_TX_VOD 20.2.2.16. XCVR_TX_VOD_PRE_EMP_CTRL_SRC
20.3. Analog Settings for Arria V GZ Devices x
20.3.1. Analog Settings for Arria V GZ Devices 20.3.2. Analog Settings Having Global or Computed Default Values for Arria V GZ Devices
20.3.1. Analog Settings for Arria V GZ Devices x
20.3.1.1. XCVR_IO_PIN_TERMINATION 20.3.1.2. XCVR_REFCLK_PIN_TERMINATION 20.3.1.3. XCVR_RX_BYPASS_EQ_STAGES_234 20.3.1.4. XCVR_TX_SLEW_RATE_CTRL 20.3.1.5. XCVR_VCCA_VOLTAGE 20.3.1.6. XCVR_VCCR_VCCT_VOLTAGE
20.3.2. Analog Settings Having Global or Computed Default Values for Arria V GZ Devices x
20.3.2.1. CDR_BANDWIDTH_PRESET 20.3.2.2. master_ch_number 20.3.2.3. PLL_BANDWIDTH_PRESET 20.3.2.4. reserved_channel 20.3.2.5. XCVR_ANALOG_SETTINGS_PROTOCOL 20.3.2.6. XCVR_RX_DC_GAIN 20.3.2.7. XCVR_RX_LINEAR_EQUALIZER_CONTROL 20.3.2.8. XCVR_RX_COMMON_MODE_VOLTAGE 20.3.2.9. XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE 20.3.2.10. XCVR_RX_SD_ENABLE 20.3.2.11. XCVR_RX_SD_OFF 20.3.2.12. XCVR_RX_SD_ON 20.3.2.13. XCVR_RX_SD_THRESHOLD 20.3.2.14. XCVR_TX_COMMON_MODE_VOLTAGE 20.3.2.15. XCVR_TX_PRE_EMP_PRE_TAP_USER 20.3.2.16. XCVR_TX_PRE_EMP_2ND_POST_TAP_USER 20.3.2.17. XCVR_TX_PRE_EMP_1ST_POST_TAP 20.3.2.18. XCVR_TX_PRE_EMP_2ND_POST_TAP 20.3.2.19. XCVR_TX_PRE_EMP_INV_2ND_TAP 20.3.2.20. XCVR_TX_PRE_EMP_INV_PRE_TAP 20.3.2.21. XCVR_TX_PRE_EMP_PRE_TAP 20.3.2.22. XCVR_TX_RX_DET_ENABLE 20.3.2.23. XCVR_TX_RX_DET_MODE 20.3.2.24. XCVR_TX_RX_DET_OUTPUT_SEL 20.3.2.25. XCVR_TX_VOD 20.3.2.26. XCVR_TX_VOD_PRE_EMP_CTRL_SRC
20.4. Analog Settings for Cyclone V Devices x
20.4.1. XCVR_IO_PIN_TERMINATION 20.4.2. XCVR_REFCLK_PIN_TERMINATION 20.4.3. XCVR_TX_SLEW_RATE_CTRL 20.4.4. XCVR_VCCR_ VCCT_VOLTAGE 20.4.5. Analog Settings Having Global or Computed Values for Cyclone V Devices
20.4.5. Analog Settings Having Global or Computed Values for Cyclone V Devices x
20.4.5.1. CDR_BANDWIDTH_PRESET 20.4.5.2. PLL_BANDWIDTH_PRESET 20.4.5.3. XCVR_ANALOG_SETTINGS_PROTOCOL 20.4.5.4. XCVR_RX_DC_GAIN 20.4.5.5. XCVR_RX_LINEAR_EQUALIZER_CONTROL 20.4.5.6. XCVR_RX_COMMON_MODE_VOLTAGE 20.4.5.7. XCVR_RX_SD_ENABLE 20.4.5.8. XCVR_RX_SD_OFF 20.4.5.9. XCVR_RX_SD_ON 20.4.5.10. XCVR_RX_SD_THRESHOLD 20.4.5.11. XCVR_TX_COMMON_MODE_VOLTAGE 20.4.5.12. XCVR_TX_PRE_EMP_1ST_POST_TAP 20.4.5.13. XCVR_TX_RX_DET_ENABLE 20.4.5.14. XCVR_TX_RX_DET_MODE 20.4.5.15. XCVR_TX_VOD 20.4.5.16. XCVR_TX_VOD_PRE_EMP_CTRL_SRC
20.5. Analog Settings for Stratix V Devices x
20.5.1. Analog PCB Settings for Stratix V Devices 20.5.2. Analog Settings Having Global or Computed Default Values for Stratix V Devices
20.5.1. Analog PCB Settings for Stratix V Devices x
20.5.1.1. XCVR_GT_IO_PIN_TERMINATION 20.5.1.2. XCVR_IO_PIN_TERMINATION 20.5.1.3. XCVR_REFCLK_PIN_TERMINATION 20.5.1.4. XCVR_RX_BYPASS_EQ_STAGES_234 20.5.1.5. XCVR_TX_SLEW_RATE_CTRL 20.5.1.6. XCVR_VCCA_VOLTAGE 20.5.1.7. XCVR_VCCR_VCCT_VOLTAGE
20.5.2. Analog Settings Having Global or Computed Default Values for Stratix V Devices x
20.5.2.1. CDR_BANDWIDTH_PRESET 20.5.2.2. master_ch_number 20.5.2.3. PLL_BANDWIDTH_PRESET 20.5.2.4. reserved_channel 20.5.2.5. XCVR_ANALOG_SETTINGS_PROTOCOL 20.5.2.6. XCVR_GT_RX_DC_GAIN 20.5.2.7. XCVR_RX_DC_GAIN 20.5.2.8. XCVR_RX_LINEAR_EQUALIZER_CONTROL 20.5.2.9. XCVR_GT_RX_COMMON_ MODE_VOLTAGE 20.5.2.10. XCVR_GT_RX_CTLE 20.5.2.11. XCVR_GT_TX_COMMON_ MODE_VOLTAGE 20.5.2.12. XCVR_GT_TX_PRE_EMP_1ST_POST_TAP 20.5.2.13. XCVR_GT_TX_PRE_EMP_ INV_PRE_TAP 20.5.2.14. XCVR_GT_TX_PRE_EMP_ PRE_TAP 20.5.2.15. XCVR_GT_TX_VOD_MAIN_TAP 20.5.2.16. XCVR_RX_COMMON_MODE_VOLTAGE 20.5.2.17. XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE 20.5.2.18. XCVR_RX_SD_ENABLE 20.5.2.19. XCVR_RX_SD_OFF 20.5.2.20. XCVR_RX_SD_ON 20.5.2.21. XCVR_RX_SD_THRESHOLD 20.5.2.22. XCVR_TX_COMMON_MODE_VOLTAGE 20.5.2.23. XCVR_TX_PRE_EMP_PRE_TAP_USER 20.5.2.24. XCVR_TX_PRE_EMP_2ND_POST_TAP_USER 20.5.2.25. XCVR_TX_PRE_EMP_1ST_POST_TAP 20.5.2.26. XCVR_TX_PRE_EMP_2ND_POST_TAP 20.5.2.27. XCVR_TX_PRE_EMP_INV_2ND_TAP 20.5.2.28. XCVR_TX_PRE_EMP_INV_PRE_TAP 20.5.2.29. XCVR_TX_PRE_EMP_PRE_TAP 20.5.2.30. XCVR_TX_RX_DET_ENABLE 20.5.2.31. XCVR_TX_RX_DET_MODE 20.5.2.32. XCVR_TX_RX_DET_OUTPUT_SEL 20.5.2.33. XCVR_TX_VOD 20.5.2.34. XCVR_TX_VOD_PRE_EMP_CTRL_SRC
21. Migrating from Stratix IV to Stratix V Devices Overview x
21.1. Differences in Dynamic Reconfiguration for Stratix IV and Stratix V Transceivers 21.2. Differences Between XAUI PHY Parameters for Stratix IV and Stratix V Devices 21.3. Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices 21.4. Differences Between PHY IP Core for PCIe PHY (PIPE) Parameters in Stratix IV and Stratix V Devices 21.5. Differences Between PHY IP Core for PCIe PHY (PIPE) Ports for Stratix IV and Stratix V Devices 21.6. Differences Between Custom PHY Parameters for Stratix IV and Stratix V Devices 21.7. Differences Between Custom PHY Ports in Stratix IV and Stratix V Devices
22. Additional Information for the Transceiver PHY IP Core x
22.1. Revision History for Previous Releases of the Transceiver PHY IP Core 22.2. How to Contact Intel
1. Introduction to the Protocol-Specific and Native Transceiver PHYs
2. Getting Started Overview
3. 10GBASE-R PHY IP Core
4. Backplane Ethernet 10GBASE-KR PHY IP Core
5. 1G/10Gbps Ethernet PHY IP Core
6. 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core
7. XAUI PHY IP Core
8. Interlaken PHY IP Core
9. PHY IP Core for PCI Express (PIPE)
10. Custom PHY IP Core
11. Low Latency PHY IP Core
12. Deterministic Latency PHY IP Core
13. Stratix V Transceiver Native PHY IP Core
14. Arria V Transceiver Native PHY IP Core
15. Arria V GZ Transceiver Native PHY IP Core
16. Cyclone V Transceiver Native PHY IP Core Overview
17. Transceiver Reconfiguration Controller IP Core Overview
18. Transceiver PHY Reset Controller IP Core
19. Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices
20. Analog Parameters Set Using QSF Assignments
21. Migrating from Stratix IV to Stratix V Devices Overview
22. Additional Information for the Transceiver PHY IP Core

22.1. Revision History for Previous Releases of the Transceiver PHY IP Core

This section provides the revision history for all versions of this user guide.
Chapter Document Version Changes Made
Transceiver Reconfiguration Controller DFE Registers 3.3 Updated to state that DFE is supported by Arria V GZ and Stratix V devices.
Stratix V Transceiver Native PHY IP Core 3.2 Corrected the definition for tx_10g_control [9<n>-1:0] in the Basic mode, 66-bit word width in Table: 10G PCS Interface Signals.
1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core 3.2 Made the following changes:
  • Updated Timing Constraints.
  • Removed a footnote from the description of the Register Map.
  • Updated Table: Register Map.
10GBASE-R PHY IP Core 3.1 Corrected Figure: Stratix V Clock Generation and Distribution.
Backplane Ethernet 10GBASE-KR PHY IP Core 3.1
  • Added the section MII Interface Signals and also listed them in Figure: 10GBASE-KR Top-Level Signals.
  • Clarified the descriptions for tx_pcfifo_error_1g and rx_pcfifo_error_1g signals.
  • Corrected the default value for ber_time_k_frames register.
  • Added the default value for ber_time_m_frames register.
  • Changed the 1GbE parameter name from Enable SGMII bridge logic to Expose MII Interface.
1G/10Gbps Ethernet PHY IP Core 3.1
  • Added the section MII Interface Signals and also listed them in Figure: 1G/10GbE PHY Top-Level Signals.
  • Added 10G PCS Pattern Generators support for 1G/10G Ethernet PHY IP core.
  • Changed the 1GbE parameter name from Enable SGMII bridge logic to Expose MII Interface.
Interlaken PHY IP Core 3.1 Clarified the rx_parallel_data<n> [65] signal description.
Custom PHY IP Core 3.1 Removed the reset_control (write) register from Table: Reset Control Registers–Automatic Reset Controller.
Stratix V Transceiver Native PHY IP Core 3.1 Corrected the definition for rx_10g_control [3] in Table: 10G PCS Interface Signals.
Arria V GZ Transceiver Native PHY IP Core 3.1 Corrected the definition for rx_10g_control [3] in Table: 10G PCS Interface Signals.
Cyclone V Transceiver Native PHY IP Core Overview 3.1 Corrected the maximum data rate in Table: PMA Options.
Analog Parameters Set Using QSF Assignments 3.1 Clarified the analog setting options for XCVR_TX_PRE_EMP_2ND_POST_TAP_USER.
Backplane Ethernet 10GBASE-KR PHY IP Core 3.0
  • Corrected the default values for the 10GBASE-KR Link Training Parameters VODMINRULE, VPOSTRULE, INITMAINVAL, INITPOSTVAL, and INITPREVAL in the Table: Link Training Settings
1G/10Gbps Ethernet PHY IP Core 3.0
  • Added the status signal led_panel_link to the Table: SGMII and GMII Signals.
  • Clarified the signal description for led_link, rx_block_lock, and COPPER_LINK_STATUS.
  • Corrected the register list for address 0x94/95 (SGMII mode) in Table: GMII PCS Registers.
Stratix V Transceiver Native PHY IP Core 3.0
  • Corrected the Slew Rate Settings.
Arria V GZ Transceiver Native PHY IP Core 3.0
  • Corrected the Slew Rate Settings.
1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core 2.9

Added this chapter.
Stratix V Transceiver Native PHY IP Core 2.9
Made the following changes:
  • Added the PRBS Verifier Inversion Offset to the Table: Offsets for the Standard PCS Pattern Generator and Verifier.
  • Added the slew rate settings for SATA sub-protocol.
Arria V GZ Transceiver Native PHY IP Core 2.9
Made the following changes:
  • Added the PRBS Verifier Inversion Offset to the Table: Offsets for the Standard PCS Pattern Generator and Verifier.
  • Added the slew rate settings for SATA sub-protocol.
Analog Parameters Set Using QSF Assignments 2.9

Corrected the XCVR_RX_DC_GAIN default setting for Stratix V devices.

10GBASE-R PHY IP Core 2.8

Corrected the Product ID for 10GBASE-R PHY IP Core in Table: 10GBASE-R Release Information.

10GBASE-KR PHY IP Core 2.8

Removed Early Access FEC Option.
1G/10Gbps Ethernet PHY IP Core 2.8

Added the device ability and partner ability registers for SGMII mode to Table: GMII PCS Registers.

PHY IP Core for PCI Express (PIPE) 2.8
Made the following changes:
  • Updated Table: Device Family Support for PHY IP Core for PCI Express with the support information for Cyclone V devices.
  • Clarified the description of rx_polarity signal in Table: Avalon-ST TX Inputs.
Custom PHY IP Core 2.8
Made the following changes:
  • Clarified the description for tx_dispval signal in Table: Avalon-ST TX Interface Signals.
  • Corrected the pattern length for PMA-PCS Interface Width (20-bit manual alignment) in Table: More Information about Word Aligner Functions.
Deterministic Latency PHY IP Core 2.8
Made the following changes:
  • Added the latency values for Arria V GZ in the Table: PMA Datapath Total Latency.
  • Clarified the information in Table: Signal Definitions for tx_parallel_data with and without 8B/10B Encoding.
  • Clarified the information in Table: Signal Definitions for rx_parallel_data with and without 8B/10B Encoding.
Stratix V Transceiver Native PHY IP Core 2.8
Made the following changes:
  • Clarified the information in Table: Signal Definitions for tx_parallel_data with and without 8B/10B Encoding.
  • Clarified the information in Table: Signal Definitions for rx_parallel_data with and without 8B/10B Encoding.
  • Corrected the description of Offset 0x135[3] in Table: Pattern Generator Registers.
Arria V Transceiver Native PHY IP Core 2.8
Made the following changes:
  • Clarified the information in Table: Signal Definitions for tx_parallel_data with and without 8B/10B Encoding.
  • Clarified the information in Table: Signal Definitions for rx_parallel_data with and without 8B/10B Encoding.
  • Added a new topic called Slew Rate Setting.
Arria V GZ Transceiver Native PHY IP Core 2.8
Made the following changes:
  • Clarified the information in Table: Signal Definitions for tx_parallel_data with and without 8B/10B Encoding.
  • Clarified the information in Table: Signal Definitions for rx_parallel_data with and without 8B/10B Encoding.
  • Corrected the description of Offset 0x135[3] in Table: Pattern Generator Registers.
  • Added a new topic called Slew Rate Setting.
Cyclone V Transceiver Native PHY IP Core 2.8
Made the following changes:
  • Clarified the information in Table: Signal Definitions for tx_parallel_data with and without 8B/10B Encoding.
  • Clarified the information in Table: Signal Definitions for rx_parallel_data with and without 8B/10B Encoding.
  • Added a new topic called Slew Rate Setting.
Transceiver PHY Reset Controller IP Core 2.8

Added the Usage Examples for pll_select section.

Analog Parameters Set Using QSF Assignments 2.8

Added the default value for XCVR_TX_VOD (Analog settings for Arria V Devices).

Getting Started Overview 2.7 Updated the chapter to indicate new IP instantiation flow using the IP Catalog.
10GBASE-R PHY IP Core 2.7 Made the following changes:
  • Updated the chapter to indicate new IP instantiation flow using the IP Catalog.
  • Changed the device family support to final for this IP core in Table 3-4 Device Family Support.
  • Changed the description of Starting Channel Number parameter in General Option Parameters section.
  • Changed the description of phy_mgmt_clk_reset signal in Table 3-15: Avalon-MM PHY Management Interface.
  • Changed the TX and RX Latency numbers for Stratix V devices in Table 3-2: Latency for TX and RX PCS and PMA in Stratix V Devices.
10GBASE-KR PHY IP Core 2.7 Made the following changes:
  • Updated the chapter to indicate new IP instantiation flow using the IP Catalog.
  • Changed the device family support to final for this IP core in Table 4-2: Device Family Support.
  • Added resource utilization numbers when FEC is used in Table 4-3: 10GBASE KR PHY Performance and Resource Utilization.
  • Changed the description of tx_invpolarity register and register address 0x22 in PMA Registers section.
  • Changed the descriptions of main_rc, post_rc, and pre_rc signals with example mappings in Dynamic Reconfiguration Interface Signals section.
1G/10Gbps Ethernet PHY IP Core 2.7 Made the following changes:
  • Updated the chapter to indicate new IP instantiation flow using the IP Catalog.
  • Changed the device family support to final for this IP core in Table 5-2: Device Family Support.
  • Removed erroneous references to 10GBBASE-KR PHY IP Core from this chapter.
  • Updated the description of rx_clkslip signal in 1G/10GbE Control and Status Interfaces.
XAUI PHY IP Core 2.7 Made the following changes:
  • Updated the description of rx_digitalreset and tx_digitalreset signals in Table 6-10: Optional Clock and Reset Signals.
  • Updated Figure 6-4: XAUI Top-Level Signals - Soft PCS and PMA.
  • Added the description of xgmii_tx_clk and xgmii_rx_clk in Table 6-10: Optional Clock and Reset Signals.
Interlaken PHY IP Core 2.7 Made the following changes:
  • Updated the chapter to indicate new IP instantiation flow using the IP Catalog.
  • Changed the device family support to final for this IP core in the Table 7-1 Device Family Support.
  • Updated the descriptions of rx_dataout_bp<n> and tx_user_clkout signals in Table 7-5: Avalon-ST RX Signals.
PHY IP Core for PCI Express 2.7 Made the following changes:
  • Updated the chapter to indicate new IP instantiation flow using the IP Catalog.
  • Changed the device family support to final for this IP core in Table 8-1: Device Family Support.
  • Updated Table 8-4: Preset Mappings to TX De-Emphasis.
Custom PHY IP Core 2.7 Made the following changes:
  • Updated the chapter to indicate new IP instantiation flow using the IP Catalog.
  • Changed the device family support to final for this IP core in Table 9-1: Device Family Support.
  • Changed the description of tx_bitslipboundaryselect signal in Optional Status Interfaces section.
  • Changed the word alignment pattern for Ethernet in Table 9-11: Presets for Ethernet Protocol.
  • Added a note related to compile warning (12020) in the description of tx_analogreset signal.
  • Corrected byte ordering pattern length for configuration 4 in Byte Order Parameters section.
Low Latency PHY IP Core 2.7 Made the following changes:
  • Updated the chapter to indicate new IP instantiation flow using the IP Catalog.
  • Changed the device family support fo final for this IP core in Table 10-1: Device Family Support.
Deterministic Latency PHY IP Core 2.7 Made the following changes:
  • Updated the chapter to indicate new IP instantiation flow using the IP Catalog.
  • Changed the device family support fo final for this IP core in Table 11-4: Device Family Support.
  • Updated Table: PMA Datapath Total Latency with actual hardware delays.
  • Removed description and figure related to using PLL feedback method to align the TX core clock with the RX core clock.
  • In Deterministic Latency PHY Delay Estimation Logic section:
    • Added description of rx_std_bitslipboundaryselect signal.
    • Added footnotes related to latency calculations in Table 11-2 and Table 11-3.
Stratix V Transceiver Native PHY IP Core 2.7 Made the following changes:
  • Updated the chapter to indicate new IP instantiation flow using the IP Catalog.
  • Changed the device family support fo final for this IP core in Table 12-1: Device Family Support.
  • Added a new topic called Slew Rate Settings.
  • Changed Enable rx_pma_bitslip port parameter to Enable rx_clkslip port in Table 12-7: RX PMA Parameters.
  • Changed the description of rx_clkslip port in Table 12-38: Native PHY Common Interfaces.
  • Changed the range of PPM detector threshold parameter to +/- 1000 in Table 12-6: RX PMA Parameters.
  • Updated the description of rx_10g_blk_sh_err signal in 10G PCS Interface section.
  • Updated the description of Enable rx_std_signaldetect port parameter with details for implementing SATA/SAS applications.
  • Updated the 10G PCS Interface section to indicate that 10G PCS interface signals are used when phase compensation FIFO is in FIFO mode.
  • Added a note to Table: Status Flag Mappings for Simplified Native PHY Interface regarding EDB and PAD characters.
Arria V Transceiver Native PHY IP Core 2.7 Made the following changes:
  • Updated the chapter to indicate new IP instantiation flow using the IP Catalog.
  • Changed the device family support to final for this IP core in Table 13-1: Device Family Support.
  • Added note related to PMA Direct mode support for Arria V devices.
  • Changed the range of PPM detector threshold parameter to +/- 1000 in Table 13-6: RX PMA Parameters.
  • Added a note related to compile warning (12020) in the description of tx_analogreset signal.
  • Added Table: Status Flap Mappings for Simplified Native PHY Interface in Rate Match FIFO Parameters section.
Arria V GZ Transceiver Native PHY IP Core 2.7 Made the following changes:
  • Updated the chapter to indicate new IP instantiation flow using the IP Catalog.
  • Changed the device family support to final for this IP core in Table 14-1: Device Family Support.
  • Changed the range of PPM detector threshold parameter to +/- 1000 in Table 14-6: RX PMA Parameters.
  • Updated the description of rx_10g_blk_sh_err signal in 10G PCS Interfaces section.
  • Updated the description of Enable rx_std_signaldetect port parameter with details for implementing SATA/SAS applications.
Cyclone V Transceiver Native PHY IP Core 2.7 Made the following changes:
  • Updated the chapter to indicate new IP instantiation flow using the IP Catalog.
  • Changed the device family support to final for this IP core in Table 15-1: Device Family Support.
  • Changed the range of PPM detector threshold parameter to +/- 1000 in Table 15-6: RX PMA Parameters.
  • Added Table: Status Flag Mappings for Simplified Native PHY Interface under Rate Match FIFO Parameters section.
Transceiver Reconfiguration Controller IP Core 2.7 Made the following changes:
  • Updated the chapter to indicate new IP instantiation flow using the IP Catalog.
  • Added an exception for Native PHY IP in the Loopback Modes section.
  • Changed the introductory sentence of MIF Reconfiguration Manage Avalon-MM Master Interface section to better describe MIF Reconfiguration Management interface.
  • Updated Table 16-18: ATX PLL Tuning Offsets and Values.
  • Updated the description of Streamer Offset Register in Table 16-24: Streamer Module Registers.
  • Created a new topic Sharing Reconfiguration Interface for Multi-Channel Transceiver Designs.
  • Modified the description of cal_busy_in signal in Table 16-5: MIF Reconfiguration Management Avalon-MM Master Interface.
  • Enhanced the verbiage of Register Based Read and Register Based Write sections.
  • Added a new section called EyeQ Usage Example.
Transceiver PHY Reset Controller IP Core 2.7 Made the following changes:
  • Updated the chapter to indicate new IP instantiation flow using the IP Catalog.
  • Changed the device family support to final in Table 17-1: Device Family Support.
  • Added description for rx_analogreset signal in Transceiver PHY Reset Controller Interfaces section.
Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices 2.7 Made the following changes:
  • Updated the chapter to indicate new IP instantiation flow using the IP Catalog.
  • Added a note to indicate that it is recommended to use fractional PLL in fractional mode as a TX PLL or for PLL cascading.
Analog Parameters Set Using QSF Assignments 2.7 Made the following changes:
  • Removed references to SATA protocol from XCVR_ANALOG_PROTOCOL QSF assignment.
  • Added a note related to data rate restriction for XCVR_RX_BYPASS_EQ_STAGES_234 assignment.
Chapter Document Version Changes Made
10GBASE-R PHY IP Core 2.6 Updated the descriptions of tx_cal_busy and rx_cal_busy interface signals.
Backplane Ethernet 10GBASE-KR PHY 2.6

Made the following changes:

  • Corrected an error in the description of pcs_mode_rc[5:0] in Table 4-17: Dynamic Reconfiguration Interface Signals. Added back the option for GigE data mode and 10G data mode with FEC.
  • Updated the descriptions of tx_cal_busy and rx_cal_busy interface signals.
  • Updated the descriptions of tm_in_trigger[3:0] and tm_out_trigger [3:0] signals in Table 4-14: Control and Status Signals.
  • Updated the descriptions of xgmii_tx_clk and xgmii_rx_clk signals in Table 4-11: XGMII and GMII Signals.
  • Updated the description of en_lcl_rxeq and rxeq_done signals in Table 4-17: Dynamic Reconfiguration Interface Signals.
  • Added a note about performing read-modify-writes for all registers in 10GBASE-KR PHY Register Definitions section.
  • Added a clarification about reset sequencer in the 10GBASE-KR PHY Clock and Reset Interfaces section on page 4-18.
  • Updated tx_clkout_1g, rx_clkout_1g, tx_coreclkin_1g, and rx_coreclkin_1g connections in Figure 4-11: Clocks for Standard and 10G PCS and TX PLLs.
1G/10GbE Ethernet PHY IP Core 2.6

Made the following changes:

  • Corrected an error in the description of pcs_mode_rc[5:0] in Table 5-15: Dynamic Reconfiguration Interface Signals. Added back the option for GigE data mode and 10G data mode with FEC.
  • Updated the descriptions of tx_cal_busy and rx_cal_busy interface signals.
  • Updated the descriptions of tm_in_trigger[3:0] and tm_out_trigger [3:0] signals in Table 5-10: Control and Status Signals.
  • Updated the descriptions of xgmii_tx_clk and xgmii_rx_clk signals in Table 5-7: SGMII and GMII signals.
  • Updated the description of en_lcl_rxeq and rxeq_done signals in Table 5-15: Dynamic Reconfiguration Interface Signals.
  • Updated the description of tx_clkout_1g signal in Table 5-6: Clock and Reset Signals.
  • Added a note about performing read-modify-writes for all registers in 1G/10GbE PHY Register Definitions section.
  • Added a clarification about reset sequencer in the 1G/10GbE PHY Clock and Reset Interfaces section on page 5-7.
  • Updated tx_clkout_1g, rx_clkout_1g, tx_coreclkin_1g, and rx_coreclkin_1g connections in Figure 5-3: Clocks for Standard and 10G PCS and TX PLLs.
XAUI 2.6

Added the statement "This register is only available in the hard XAUI implementation" for 0x82 and 0x83, polarity inversion" for 0x082 and 0x083, polarity inversion registers.

Custom PHY IP Core 2.6

Made the following changes:

  • Corrected the description of tx_datak signal in Table 9-12: Avalon -ST TX Interface Signals.
  • Corrected the available word alignment pattern lengths for 20 bit PMA-PCS interface width in manual mode in Table 9-6: More Information About Word Aligner Functions.
  • Updated the descriptions of tx_cal_busy and rx_cal_busy interface signals.
Low Latency PHY IP Core 2.6 Updated the descriptions of tx_cal_busy and rx_cal_busy interface signals.
Deterministic Latency PHY IP Core 2.6

Made the following changes:

  • Corrected the description of tx_datak signal in Table 11-8: Avalon-ST TX Interface.
  • Updated the descriptions of tx_cal_busy and rx_cal_busy interface signals.
Stratix V Transceiver Native PHY IP Core 2.6

Made the following changes:

  • Removed the description for rx_clklow and rx_fref ports from Table 12-38: Native PHY Common Interfaces.
  • Removed the ports rx_clklow and rx_fref from Figure 12-5: Stratix V Native PHY Common Interfaces.
  • Updated the description of rx_10g_clk33out clock signal in Table 12-44: Name Dir Synchronous to tx_10g_coreclkin/rx_10g_coreclkin Description.
  • Updated the description of tx_pma_qpipullup ,tx_pma_qpipulldn , and rx_pma_qpipulldn signals in Table 12:38 - Native PHY Common Interfaces.
  • Updated the descriptions of tx_cal_busy and rx_cal_busy interface signals.
  • Addedext_pll_clk signal to Figure 12-5: Stratix V Native PHY Common Interfaces and added its description in Table 12-38: Native PHY Common Interfaces.
Arria V Transceiver Native PHY IP Core 2.6

Made the following changes:

  • Removed the description for rx_clklow and rx_fref ports from Table 13-31: Native PHY Common Interfaces.
  • Removed the ports rx_clklow and rx_fref from Figure 13-3: Native PHY Common Interface Ports.
  • Updated the descriptions of tx_cal_busy and rx_cal_busy interface signals.
  • Addedext_pll_clk signal to Figure 13-3: Common Interface ports and added its description in Table 13-18: Native PHY Common Interfaces.
Arria V GZ Transceiver Native PHY IP Core 2.6

Made the following changes:

  • Removed the description for rx_clklow and rx_fref ports from Table 14-38: Native PHY Common Interfaces.
  • Removed the ports rx_clklow and rx_fref from Figure 14-5: Arria V GZ Native PHY Common Interfaces.
  • Updated the description of rx_10g_clk33out clock signal in Table 14-44: Name Dir Synchronous to tx_10g_coreclkin/rx_10g_coreclkin Description.
  • Updated the description of tx_pma_qpipullup, tx_pma_qpipulldn, and rx_pma_qpipulldn signals in Table 14:38 - Native PHY Common Interfaces.
  • Updated the descriptions of tx_cal_busy and rx_cal_busy interface signals.
  • Addedext_pll_clk signal to Figure 14-5: Common Interfaces Ports and added its description in Table 14-38: Native PHY Common Interfaces.
Cyclone V Transceiver Native PHY IP Core 2.6

Made the following changes:

  • Removed the description for rx_clklow and rx_fref ports from Table 15-15: Native PHY Common Interfaces.
  • Removed the ports rx_clklow and rx_fref from Figure 15-3: Common Interfaces Ports.
  • Updated the descriptions of tx_cal_busy and rx_cal_busy interface signals.
  • Added ext_pll_clk signal to Figure 15-3: Common Interface Ports and added its description in Table 15-15: Native PHY Common Interfaces.
Transceiver Reconfiguration Controller IP Core Overview 2.6

Made the following changes:

  • Added a footnote for the Polarity register in Table 16-12: EyeQ Offsets and Values.
  • Updated the description of Control register in Table 16-18: ATX PLL Tuning Offsets and Values to clarify the conditions when tx_cal_busy gets asserted.
  • Removed physical channel address register description from all the tables describing reconfiguration registers for different blocks.
  • Updated all instances of the note about undefined register bits.
  • Updated the description of tx_cal_busy and rx_cal_busy interface signals.
Analog Parameters Set Using QSF Assignments 2.6

Made the following changes:

  • Corrected values for XCVR_REFCLK_PIN_TERMINATION. DC_COUPLING_INTERNAL_100_OHM should be DC_COUPLING_INTERNAL_100_OHMS.
  • Removed the options for XCVR_TX_COMMON_MODE_VOLTAGE and XCVR_RX_COMMON_MODE_VOLTAGE assignments and added a note to use these assignments for Arria V, Arria V GZ, Cyclone V, and Stratix V devices.
  • Removed the options for XCVR_GT_TX_COMMON_MODE_VOLTAGE and XCVR_GT_RX_COMMON_MODE_VOLTAGE and added a note to use these assigments for Stratix V GT devices.
Chapter Document Version Changes Made
Introduction 2.5 Added information on running ip-make-simscript for designs including multiple transceiver PHYs.
10GBASE-R PHY 2.5 Made the following changes:
  • Corrected description of Table 3-2 Latency for TX and RX PCS and PMA in Stratix V Devices. The FPGA fabric to PCS interface width is 64 bits.
  • Added the description for a new parameter - PCS / PMA interface width in General Option Parameters section.
  • Added frequency for rx_recovered_clk[<n>:0] . It's 257.8 MHz.
  • Updated the descriptions of rx_latency_adj_10g and tx_latency_adj_10g. Changed the width of these signals for all references.
  • Added description for Enable embedded reset controller parameter General Option Parameters section.
  • Added a new section Optional Reset Control and Status Interface.
Backplane Ethernet 10GBASE-KR PHY 2.5 Made the following changes:
  • Updated the descriptions of xgmii_tx_clk and xgmii_rx_clk in 10GBASE-KR PHY Data Interfaces section.
  • Updated the descriptions of rx_latency_adj_1g and tx_latency_adj_1g. Changed the width of these signals for all references.
  • Added SDC Timing Constraints topic.
  • Added parameter description for Use M20K for FEC Buffer (if available).
1G/10GbE Ethernet PHY IP Core 2.5 Made the following changes:
  • Corrected definition of gxmii_rx_d. This signal is synchronous to tx_clkout_1g.
  • Added frequency for rx_recovered_clk[<n>:0] . It's 257.8 MHz.
  • Updated the descriptions of rx_latency_adj_1g and tx_latency_adj_1g. Changed the width of these signals for all references.
XAUI 2.5 Made the following changes:
  • Added fact that both bits of the reset_control register at 0x042 self-clear.
  • Added SDC Timing Constraints topic.
Interlaken 2.5 Added additional information about SDC timing constraints.
PHY IP Core for PCI Express 2.5 Made the following changes:
  • Removed the reference and description for tx_invpolarity and rx_invpolarity registers from Register Interface and Register Descriptions section.
Custom PHY IP Core 2.5 Made the following changes:
  • Added information on bit mapping for tx_parallel_data and rx_parallel_data.
  • Changed the introduction of Optional Status Interfaces section. This section applies for both TX and RX.
  • Added a note related to auto-negotiation state machine in Rate Match FIFO Parameters section.
  • Updated the description of rx_bitslip signal.
  • Added SDC Timing Constraints topic.
Low Latency PHY IP Core 2.5 Added SDC Timing Constraints topic.
Deterministic Latency PHY IP Core 2.5 Made the following changes:
  • Updated the Channel Placement and Utilization for Deterministic Latency PHY with details for Arria V and Arria V GZ devices.
  • Updated the table for "Signal Definitions for rx_parallel_data with and without 8B/10B Encoding".
  • Added SDC Timing Constraints topic.
Stratix V Transceiver Native PHY IP Core 2.5 Made the following changes:
  • Corrected Figure 12-4 showing the 10G PCS datapath. This datapath does not include hard IP blocks to implement KR-FEC.
  • Corrected errors in Standard PCS Pattern Generators section.
  • Updated the description of Number of TX PLLs parameter in "TX PMA Parameters" table.
  • Updated the description of Selected Clock Network parameter in "TX PLL Parameters" table.
  • Added a note related to auto-negotiation state machine in Rate Match FIFO Parameters section.
  • Updated the description of rx_std_bitslip signal.
  • Added information on PRBS-8 Standard PCS pattern generator.
Arria V Transceiver Native PHY IP Core 2.5 Made the following changes:
  • Updated the description of Number of TX PLLs parameter in "TX PMA Parameters" table.
  • Updated the description of Selected Clock Network parameter in "TX PLL Parameters" table.
  • Added a note related to auto-negotiation state machine in Rate Match FIFO Parameters section.
  • Updated the description of rx_std_bitslip signal.
  • Updated the table for "Signal Definitions for rx_parallel_data with and without 8B/10B Encoding".
Arria V GZ Transceiver Native PHY IP Core 2.5 Made the following changes:
  • Updated the description of Number of TX PLLs parameter in "TX PMA Parameters" table.
  • Updated the description of Selected Clock Network parameter in "TX PLL Parameters" table.
  • Updated the table for "Signal Definitions for rx_parallel_data with and without 8B/10B Encoding".
  • Added a note related to auto-negotiation state machine in Rate Match FIFO Parameters section.
  • Updated the description of rx_std_bitslip signal.
Cyclone V Transceiver Native PHY IP Core 2.5 Made the following changes:
  • Updated the description of Number of TX PLLs parameter in "TX PMA Parameters" table.
  • Updated the description of Selected Clock Network parameter in "TX PLL Parameters" table.
  • Added a note related to auto-negotiation state machine in Rate Match FIFO Parameters section.
Transceiver Reconfiguration Controller IP Core Overview 2.5 Made the following changes:
  • Updated table for "Device Support for Dynamic Reconfiguration" to indicate that Arria® V and Cyclone ® V devices support TX PLL switching.
  • Added a note in table for "PMA Offsets and Values" to indicate possible methods to modify RX linear equalization settings.
  • Added a note related to PLL reference clock status in Transceiver Reconfiguration Controller DFE Registers section and ATX PLL Calibration section.
  • Updated the description of mgmt_clk_clk signal in Reconfiguration Management Interfaces section.
  • Changed the name of "one time adaptation mode" to "triggered dfe mode" and updated the Controlling DFE Using Register-Based Reconfiguration section.
  • Added a note in Transceiver Reconfiguration Controller EyeQ Registers section.
  • Added a note related to default values in Transceiver Reconfiguration Controller EyeQ Registers section.
Transceiver Reset Controller IP Core Overview 2.5 Made the following changes:
  • Updated the description of rx_manual signal in Interfaces for Transceiver PHY Reset Controller section.
  • Updated the description of pll_select signal.
  • Added a new section "Usage Examples for pll_select".
Analog Parameters Set Using QSF Assignments 2.5 Made the following changes:
  • Updated definitions of XCVR_RX_SD_ENABLE, XCVR_RX_SD_OFF, XCVR_RX_SD_ON, and XCVR_RX_SD_THRESHOLD.These settings are now available for SATA and SAS in addition to PCIe PIPE.
  • Added documentation for XCVR_ANALOG_SETTINGS_PROTOCOL setting.
  • Added warnings that there are restrictions XCVR_TX_VOD, XCVR_TX_PRE_EMP_1ST_POST_TAP, XCVR_TX_PRE_EMP_2ND_POST_TAP, and XCVR_TX_PRE_EMP_PRE_TAP for Stratix V and Arria V GZ devices.
  • Added warnings for restrictions on XCVR_TX_PRE_EMP_1ST_POST_TAP for Arria V and Cyclone V devices.
  • Changed default value for XCVR_TX_VOD_PRE_EMP_CTRL_SRC It's DYNAMIC_CTL for PCIe and RAM_CTL for other protocols.
  • Corrected example showing how to override the master_ch_number. The override must be applied to the transceiver instance, not the top-level PHY wrapper.
Date Document Version Changes Made
1G/10Gbps Ethernet PHY IP Core 2.4
Backplane Ethernet 10GBASE-KR PHY IP Core 2.4 Added descriptions of FEC-related bits: C2[8], CB[26:25].
PHY IP Core for PCI Express (PIPE) 2.4
Date Document Version Changes Made
1G/10Gbps Ethernet PHY IP Core 2.3 Changed speed of rx_recovered_clk from 125 MHz or 156.25 MHz to 125 MHz or 257.8125 MHz .
Backplane Ethernet 10GBASE-KR PHY IP Core 2.3 Changed speed of rx_recovered_clk from 125 MHz or 156.25 MHz to 125 MHz or 257.8125 MHz .
PHY IP Core for PCI Express (PIPE) 2.3 Added definition for pipe_tx_data_valid
Date Document Version Changes Made
PHY IP Core for PCI Express 2.2 Corrected SDC timing constraint for 62.5 MHz. Clock name is clk_g1.
Stratix V Native PHY 2.2 Correction: You can specify PLL merging using the XCVR_TX_PLL_RECONFIG_GROUP QSF setting, not the FORCE_MERGE_PLL QSF setting.
Arria V Native PHY 2.2 Correction: You can specify PLL merging using the XCVR_TX_PLL_RECONFIG_GROUP QSF setting, not the FORCE_MERGE_PLL QSF setting.
Arria V GZ Native PHY 2.2 Correction: You can specify PLL merging using the XCVR_TX_PLL_RECONFIG_GROUP QSF setting, not the FORCE_MERGE_PLL QSF setting.
Cyclone V Native PHY 2.2 Correction: You can specify PLL merging using the XCVR_TX_PLL_RECONFIG_GROUP QSF setting, not the FORCE_MERGE_PLL QSF setting.
Transceiver Reconfiguration Controller
May 2013 2.2 Update to Transceiver Reconfiguration Controller chapter. Table 16-3 showing resource utilization for Stratix V devices, the timing unit should be us, microseconds, not ms, milliseconds.
Date Document Version Changes Made
Introduction
April 2013 2.1 Update to introduction. Renamed heading "Additional Transceiver PHYs" to "Non-Protocol-Specific Transceiver PHYs."
Getting Started
April 2013 2.1 No changes from previous release.
10GBASE-R
April 2013 2.1 No changes from previous release.
10GBASE-KR
April 2013 2.1 No changes from previous release.
1Gbe/10GbE
April 2013 2.1 No changes from previous release.
XAUI
April 2013 2.1 Fixed minor topographical error in heading.
Interlaken
April 2013 2.1 No changes from previous release.
PHY IP Core for PCI Express
April 2013 2.1 No changes from previous release.
Custom PHY
April 2013 2.1 No changes from previous release.
Low Latency PHY
April 2013 2.1 No changes from previous release.
Deterministic Latency PHY
April 2013 2.1 No changes from previous release.
Stratix V Native PHY
April 2013 2.1 Removed Arria V GT sentence on first page.
Arria V Native PHY
April 2013 2.1 No changes from previous release.
Arria V GZ Native PHY
April 2013 2.1 Removed Arria V GT sentence on first page.
Cyclone V Native PHY
April 2013 2.1 No changes from previous release.
Transceiver Reconfiguration Controller
April 2013 2.1 Rename table 16-13 to DFE Registers. Fix typo in Reconfig Addr column changed 7’h11 to 7’h19. In Table 16-8, removed the DCD Calibration registers row.
Transceiver Reset Controller
April 2013 2.1 No changes from previous release.
Transceiver PLL for Arria V, Arria V GZ, and Stratix V Devices
April 2013 2.1 No changes from previous release.
Analog Parameters Set Using QSF Assignment
April 2013 2.1 Fix typo in the "Analog Settings for Arria V GZ Devices" table.
Migrating from Stratix IV to Stratix V Devices
April 2013 2.1 No changes from previous release.
Date Document Version Changes Made
Introduction
March 2013 2.0 No changes from previous release.
Getting Started
March 2013 2.0 No changes from previous release.
10GBASE-R
March 2013 2.0 No changes from previous release.
10GBASE-KR
March 2013 2.0 Made the following changes:
  • Improved the description of automatic speed detection.
  • Updated speed grade information.
  • Updated definition of KR AN Link Ready[5:0] to include 1000BASE-KX.
  • Added the following registers SEQ LT timeout at 0xB1, Bit 2 and SEQ Reconfig Mode[5:0] 0xB1, Bits[13:8] registers
  • Revised Functional Description section.
  • Corrected typos in specifications of address bits Ovride LP Coef enable , Updated TX Coef newand Updated RX coef new .
  • Corrected encodings for ber_time_k_frames, ber_time_frames and ber_time_m_frames.
1Gbe/10GbE
March 2013 2.0 Made the following changes:
  • Updated speed grade information.
  • Removed definition of Disable AN Timer bit. It is not used for this variant.
  • Added fact that RESTART_AUTO_NEGOTIATION bit is self-clearing (0x90, bit 9)
  • Added fact that half-duplex mode is not supported. (0x94, bit 6)
  • Added fact that the next page bit is not supported. (0x94, bit 15)
XAUI
March 2013 2.0 Added Arria V, Arria V GZ and Cyclone V to the list of devices that do not support the pma_tx_pll_is_locked register in Table 6-15: XAUI PHY IP Core Registers.
Interlaken
March 2013 2.0 No changes from previous release.
PHY IP Core for PCI Express
March 2013 2.0 Added SDC constraints for Gen3 clocking.
Custom PHY
March 2013 2.0 No changes from previous release.
Low Latency PHY
March 2013 2.0 No changes from previous release.
Deterministic Latency PHY
March 2013 2.0 No changes from previous release.
Stratix V Native PHY
March 2013 2.0 Updated definition of User external TX PLL to include information on how to instantiate an external PLL.
Arria V Native PHY
March 2013 2.0 Updated definition of User external TX PLL to include information on how to instantiate an external PLL.
Arria V GZ Native PHY
March 2013 2.0 Updated definition of User external TX PLL to include information on how to instantiate an external PLL.
Cyclone V Native PHY
March 2013 2.0 Updated definition of User external TX PLL to include information on how to instantiate an external PLL.
Transceiver Reconfiguration Controller
March 2013 2.0 Made the following changes:
  • Updated definition ofTX PLL select at 0x4 in Table 16-21: PLL Reconfiguration Offsets and Values.
  • Changed Figure 16-5: MIF File Formatto match data in Table 16-26.
  • Changed Example 16-11 to read the busy bit after each command, read_32 0x3a.
  • Added SDC timing constraints.
  • Changed RX Equalization Control0x11 in Table 16-10: PMA Offsets and Values to RW. This change is available starting with Quartus II 12.1 SP1.
  • Clarified encodings for RX equalization DC gain in Table 16-10: PMA Offsets and Values.
  • Clarified encodings for pre-emphasis pre-tap and pre-emphasis second post-tap in Table 16-10: PMA Offsets and Values.
  • Clarified fact that you can only connect a single Transceiver Reconfiguration Controller to a single transceiver PHY.
  • Updated recommendations for use of DCD in Arria V and Cyclone V devices. You should use DCD if the data rate is greater than 4.9152 Gbps or if there is dynamic TX PLL switching and the data rate is greater than 4.9152 Gbps. Updated address map and illustration to include DCD function.
Transceiver Reset Controller
March 2013 2.0 Added tx_ready and rx_ready to Figure 17-1.
Transceiver PLL for Arria V, Arria V GZ, and Stratix V Devices
March 2013 2.0 Initial Release.
Analog Parameters Set Using QSF Assignment
March 2013 2.0 Made the following changes.
  • Changed choices for XCVR_RX_SD_ENABLE from TRUE/FALSE to On/Off
  • Corrected definitions of XCVR_IO_PIN_TERMINATION and XCVR_GT_IO_PIN_TERMINATION which were reversed.
  • Added references to Knowledge Base Solution showing the mapping of Transceiver Toolkit settings to XCVR_TX_PRE_EMP_PRE_TAP, XCVR_TX_PRE_EMP_INV_PRE_TAP and XCVR_TX_PRE_EMP_PRE_TAP_USER for Arria V GZ and Stratix V devices.
  • Added references to Knowledge Base Solution showing the mapping of Transceiver Toolkit settings to XCVR_TX_PRE_EMP_2ND_POST_TAP, XCVR_TX_PRE_EMP_INV_2ND_TAP, and XCVR_TX_PRE_EMP_2ND_POST_TAP_USER for Arria V GZ and Stratix V devices.
Migrating from Stratix IV to Stratix V Devices
March 2013 2.0 No changes from previous release.
Date Document Version Changes Made
Introduction and Getting Started
February 2013 1.9
  • Reformatted.
10GBASE-R PHY
February 2013 1.9
  • Reformatted.
  • Corrected definition of the PLL type parameter. Altera recommends the ATX PLL for data rates greater than 8 Gbps.
Backplane Ethernet 10GBASE-KR PHY
February 2013 1.9
  • Reformatted.
  • Removed description of PMA reset_ch_bitmask at 0x41 which is not available. Added definition of digital and analog resets at 0x44, bits 1-3.
  • Removed definitions of trn_in_trigger and trn_out_trigger buses which are not used.
  • Corrected direction of xgmii_rx_clk in pinout figure.
1G/10GbE PHY
February 2013 1.9
  • Reformatted.
  • Corrected definition of rx_data_ready. This signal is used and indicates that the PCS is ready to receive data.
  • Removed description of PMA reset_ch_bitmask at 0x41 and reset_control at 0x42 which are not available.
  • Removed definitions of trn_in_trigger and trn_out_trigger buses which are not used.
XAUI PHY
February 2013 1.9
  • Reformatted.
Interlaken PHY
February 2013 1.9
  • Reformatted.
  • Improved definitions of rx_parallel_data<n>[68], rx_dataout_bp<n> and typo in definition of tx_user_clkout.
PHY IP Core for PCI Express (PIPE)
February 2013 1.9
  • Reformatted.
Custom PHY
February 2013 1.9
  • Reformatted.
Low Latency PHY
February 2013 1.9
  • Reformatted.
Deterministic Latency PHY
February 2013 1.9
  • Reformatted.
  • Corrected headings in Table 11-4. The TX PMA Latency in UI and RX PMA Latency in UI were previously reversed.
  • In Table 11-3, added explanation of a latency uncertainty of 0.5 cycles when the byte serializer/deserializer is turned on. The location of the alignment pattern which can be in the upper or lower symbol.
Stratix V Native PHY
February 2013 1.9
  • Reformatted.
  • Added missing descriptions of Interlaken parameters to 10G RX FIFO section.
  • Improved definition of pll_powerdown signal.
Arria V Native PHY
February 2013 1.9
  • Reformatted.
  • Removed QPI signals from Figure showing Arria V Native PHY Common Interfaces. These signals are not available for Arria V devices.
  • Removed SDC constraints for 10G signals which are not available for Arria V.
Arria V GZ Native PHY
February 2013 1.9
  • Reformatted.
  • Improved definition of pll_powerdown signal.
Cyclone V Native PHY
February 2013 1.9
  • Reformatted.
  • Removed information about PMA direct mode. PMA direct mode is not supported for Cyclone V devices.
  • Improved definition of pll_powerdown signal.
Transceiver Reconfiguration Controller
February 2013 1.9
  • Reformatted.
  • Expanded definition of mgmt_clk_clk to include constraints when CvP is enabled and frequency range for Arria V GZ and Cyclone V devices.
  • Corrected address for channel 2 in register-based read examples.
Transceiver PHY Reset Controller
February 2013 1.9
  • Reformatted.
  • Improved definition of pll_powerdown and rx_manualsignals.
Analog Parameters Set Using QSF Assignments
February 2013 1.9
  • Reformatted.
  • Added the following settings to the Arria V and Cyclone V tables: XCVR_RX_SD_ON, XCVR_RX_SD_OFF, XCVR_RX_SD_THRESHOLD, CDR_BANDWIDTH_PRESET, XCVR_RX_COMMON_MODE_VOLTAGE, XCVR_TX_COMMON_MODE_VOLTAGE, XCVR_TX_RX_DET_ENABLE, and XCVR_RX_DET_MODE.
Migrating from Stratix IV to Stratix V Devices
February 2013 1.9
  • Reformatted.
Introduction
November 2012 1.8
  • Expanded discussion of the Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Native PHY IP Cores.
  • Added Riviera-PRO Aldec simulation directory.
10GBASE-R PHY
November 2012 1.8
  • Added support for IEEE 1588 Precision Time Protocol.
  • Added Arria V GZ support.
  • Enabled RCLR_BER_COUNT (0x81, bit 3) and HI_BER (0x82, bit 1) for Arria V GZ and Stratix V devices.
  • Moved Analog Options to a separate chapter.
10GBASE-KR PHY
November 2012 1.8
  • Initial release.
1G/10 Gbps Ethernet PHY
November 2012 1.8
  • Initial release.
XAUI PHY
November 2012 1.8
  • Added Arria V GZ support.
  • Moved Analog Options to a separate chapter.
  • Added constraint for tx_digitalreset when TX PCS uses bonded clocks.
Interlaken PHY
November 2012 1.8
  • Added Arria V GZ support.
  • Added 12500 Mbps lane rate.
  • Moved Analog Options to a separate chapter.
  • Removed recommendation to use /40 for tx_user_clkout and rx_coreclkin. Data rates between /40 and /67 all work reliably.
PHY IP Core for PCI Express (PIPE)
November 2012 1.8
  • Added Gen3 support.
  • Added Arria V GZ support.
  • Added ×2 support.
  • Added discussion of link equalization for Gen3.
  • Added timing diagram showing rate change to Gen3.
  • Revised presentation of signals.
  • Corrected the definition of rx_eidleinfersel[3<n>-1:0].
  • Moved Analog Options to a separate chapter.
  • Updated section on Logical Lane Assignment Restrictions.
  • Removed the following statement from the definition of pll_powerdown. Asserting pll_powerdown no longer powers down tx_analogreset. tx_analogreset is a separate signal.
Custom PHY IP Core
November 2012 1.8
  • Added Cyclone V support.
  • Moved Analog Options to a separate chapter.
  • Added constraint for tx_digitalreset when TX PCS uses bonded clocks.
  • Corrected description of manual word alignment mode.
Low Latency PHY IP Core
November 2012 1.8
  • Added Cyclone V support.
  • Moved Analog Options to a separate chapter.
  • Added constraint for tx_digitalreset when TX PCS uses bonded clocks.
  • Added RX bitslip option for the word aligner when the 10G PCS is selected.
  • Added description of reset_fine_control register at 0x044. This register is available when not using the embedded reset controller.
Deterministic Latency PHY IP Core
November 2012 1.8
  • Added Cyclone V support.
  • Moved Analog Options to a separate chapter.
Stratix V Transceiver Native PHY
November 2012 1.8
  • Added support for Standard and 10G datapaths.
  • Added QPI interface.
  • Moved Analog Options to a separate chapter.
  • Added constraint for tx_digitalreset when TX PCS uses bonded clocks.
Arria V Transceiver Native PHY
November 2012 1.8
  • Added support for Standard datapath.
  • Added support for multiple PLLs.
  • Moved Analog Options to a separate chapter.
  • Added constraint for tx_digitalreset when TX PCS uses bonded clocks.
Arria V GZ Transceiver Native PHY
November 2012 1.8
  • Initial release.
Cyclone V Transceiver Native PHY
November 2012 1.8
  • Initial release.
Reconfiguration Controller
November 2012 1.8
  • Added MIF addressing mode option. Byte and word (16 bits) addressing are available.
  • Added ATX PLL reference clock switching and reconfiguration of ATX PLL settings, including counters.
  • Added support for ATX PLL reconfiguration.
  • Added statement that if you are using the EyeQ monitor when DFE is enabled, if you must use the EyeQ monitor with a 1D-eye.
  • Corrected definition of DFE_control bit at 0xa. This register is write only.
  • Removed duty cycle calibration. This function is run automatically during the power-on sequence.
  • Added DFE support including examples showing how to program this function.
  • Added DCD for Arria V devices.
  • Updated data for writes in Streamer Mode 1 Reconfiguration.
  • Changed data value to write in step 7 of Streamer-Based Reconfiguration.
  • Changed data value to write to setup streaming in Reconfiguration of Logical Channel 0 Using a MIF.
Transceiver PHY Reset Controller
November 2012 1.8
  • Added Arria V GZ support.
  • Added SDC constraint for tx_digitalreset when TX PCS uses bonded clocks.
Analog Parameters Set Using QSF Assignments
November 2012 1.8
  • Created separate chapter for analog parameters that were previously listed in the individual transceiver PHY chapters.
  • Changed default value for XCVR_GT_RX_COMMON_MODE_VOLTAGE to 0.65V.
Introduction and Getting Started
June 2012 1.7
  • Added brief discussion of the Stratix V and Arria V Transceiver Native PHY IP Cores.
Getting Started
June 2012 1.7
  • No changes from the previous release.
10GBASE-R PHY
June 2012 1.7
  • Added the following QSF settings to all transceiver PHY: XCVR_TX_PRE_EMP_PRE_TAP_USER, XCVR_TX_PRE_EMP_2ND_POST_TAP_USER, and 11 new settings for GT transceivers.
  • Added Arria V device support.
  • Changed the default value for XCVR_REFCLK_PIN_TERMINATION from DC_coupling_internal_100_Ohm to AC_coupling.
  • Changed references to Stratix IV GX to Stratix IV GT. This IP core only supports Stratix IV GT devices.
  • Added optional pll_locked status signal for Arria V and Stratix V devices. Added optional rx_coreclkin.
  • Added arrows Transceiver Reconfiguration Controller IP Core connection to block diagram.
  • Changed the maximum frequency of phy_mgmt_clk to 150 MHz if the same clock is used for the Transceiver Reconfiguration Controller IP Core.
  • Added the following restriction in the dynamic reconfiguration section: three channels share an Avalon-MM slave interface which must connect to the same Transceiver Reconfiguration Controller IP Core.
  • Added example showing how to override the logical channel 0 channel assignment in Stratix V devices.
  • Added table showing latency through PCS and PMA for Arria V and Stratix V devices.
XAUI PHY
June 2012 1.7
  • Added the following QSF settings to all transceiver PHY: XCVR_TX_PRE_EMP_PRE_TAP_USER, XCVR_TX_PRE_EMP_2ND_POST_TAP_USER, and 11 new settings for GT transceivers.
  • Added reference Transceiver device handbook chapters for detailed explanation of PCS blocks.
  • Changed the default value for XCVR_REFCLK_PIN_TERMINATION from DC_coupling_internal_100_Ohm to AC_coupling.
  • Changed the maximum frequency of phy_mgmt_clk to 150 MHz if the same clock is used for the Transceiver Reconfiguration Controller IP Core.
  • Added example showing how to override the logical channel 0 channel assignment in Stratix V devices.
  • Expanded definition of External PMA control and configuration parameter.
  • Added the following restriction in the dynamic reconfiguration section: three channels share an Avalon-MM slave interface which must connect to the same Transceiver Reconfiguration Controller IP Core.
  • Added note that cal_blk_powerdown register is not available for Stratix V devices.
Interlaken PHY
June 2012 1.7
  • Added support for custom, user-defined, data rates.
  • Added the following QSF settings to all transceiver PHY: XCVR_TX_PRE_EMP_PRE_TAP_USER, XCVR_TX_PRE_EMP_2ND_POST_TAP_USER, and 11 new settings for GT transceivers.
  • Changed the default value for XCVR_REFCLK_PIN_TERMINATION from DC_coupling_internal_100_Ohm to AC_coupling.
  • Updated the definition of tx_sync_done. It is no longer necessary to send pre-fill data before tx_sync_done and tx_ready are asserted.
  • Updated definition of tx_datain_bp<n>.
  • Added arrows indicating Transceiver Reconfiguration Controller IP Core connection to block diagram.
  • Changed the maximum frequency of phy_mgmt_clk to 150 MHz if the same clock is used for the Transceiver Reconfiguration Controller IP Core.
  • Clarified signal definitions.
  • Added the following restriction in the dynamic reconfiguration section: three channels share an Avalon-MM slave interface which must connect to the same Transceiver Reconfiguration Controller IP Core.
PHY IP Core for PCI Express (PIPE)
June 2012 1.7
  • Added the following QSF settings to all transceiver PHY: XCVR_TX_PRE_EMP_PRE_TAP_USER, XCVR_TX_PRE_EMP_2ND_POST_TAP_USER, and 11 new settings for GT transceivers.
  • Added reference Stratix V Transceiver Architecture chapter for detailed explanation of PCS blocks.
  • Changed the default value for XCVR_REFCLK_PIN_TERMINATION from DC_coupling_internal_100_Ohm to AC_coupling.
  • Corrected definition of tx_bitslipboundary_select register.
  • Changed pipe_rate signal to 2 bits.
  • Added the following restriction in the dynamic reconfiguration section: three channels share an Avalon-MM slave interface which must connect to the same Transceiver Reconfiguration Controller IP Core.
Custom PHY IP Core
June 2012 1.7
  • Added the following QSF settings to all transceiver PHY: XCVR_TX_PRE_EMP_PRE_TAP_USER, XCVR_TX_PRE_EMP_2ND_POST_TAP_USER, and 11 new settings for GT transceivers.
  • Added reference to Stratix V Transceiver Architecture chapter for detailed explanation of the PCS blocks.
  • Updated definition of rx_enapatternalign: It is edge sensitive in most cases; however, if the PMA-PCS interface width is 10 bits, it is level sensitive.
  • Added definition for rx_byteordflag output status signal which is created when you enable the byte ordering block.
  • Changed the default value for XCVR_REFCLK_PIN_TERMINATION from DC_coupling_internal_100_Ohm to AC_coupling.
  • Added arrows indicating Transceiver Reconfiguration Controller IP Core connection to block diagram.
  • Changed the maximum frequency of phy_mgmt_clk to 150 MHz if the same clock is used for the Transceiver Reconfiguration Controller IP Core.
  • Added the following restriction in the dynamic reconfiguration section: three channels share an Avalon-MM slave interface which must connect to the same Transceiver Reconfiguration Controller IP Core.
Low Latency PHY IP Core
June 2012 1.7
  • Added the following QSF settings to all transceiver PHY: XCVR_TX_PRE_EMP_PRE_TAP_USER, XCVR_TX_PRE_EMP_2ND_POST_TAP_USER, and 11 new settings for GT transceivers.
  • Changed the default value for XCVR_REFCLK_PIN_TERMINATION from DC_coupling_internal_100_Ohm to AC_coupling.
  • Added arrows indicating Transceiver Reconfiguration Controller IP Core connection to block diagram.
  • Changed the maximum frequency of phy_mgmt_clk to 150 MHz if the same clock is used for the Transceiver Reconfiguration Controller IP Core.
  • Added the following restriction in the dynamic reconfiguration section: three channels share an Avalon-MM slave interface which must connect to the same Transceiver Reconfiguration Controller IP Core.
Deterministic Latency PHY IP Core
June 2012 1.7
  • Added the following QSF settings to all transceiver PHY: XCVR_TX_PRE_EMP_PRE_TAP_USER, XCVR_TX_PRE_EMP_2ND_POST_TAP_USER, and 11 new settings for GT transceivers.
  • Added PLL reconfiguration option.
  • Changed the default value for XCVR_REFCLK_PIN_TERMINATION from DC_coupling_internal_100_Ohm to AC_coupling.
  • Removed references to the byte serializer and deserializer which is not included in the datapath.
  • Added GUI option for tx_clkout feedback path for TX PLL to align the TX and RX clock domains and figure illustrating this approach.
  • Added tables showing the signals in TX and RX parallel data that correspond to data, control, and status signals with and without 8B/10B encoding.
  • Corrected definition of rx_runnindisp. This is a status output.
  • Added the following restriction in the dynamic reconfiguration section: three channels share an Avalon-MM slave interface which must connect to the same Transceiver Reconfiguration Controller IP Core.
Stratix V Transceiver Native PHY
June 2012 1.7
  • Initial release.
Arria V Transceiver Native PHY
June 2012 1.7
  • Initial release.
Transceiver PHY Reconfiguration Controller
June 2012 1.7
  • DFE now automatically runs offset calibration and phase interpolator (PI) phase calibration at power on.
  • Added section explaining how to generate a reduced MIF file.
  • Corrected definition of EyeQ control register. Writing a 1 to bit 0 enables the Eye monitor.
  • Corrected bit-width typos in PMA Analog Registers.
Transceiver PHY Reset Controller
June 2012 1.7
  • Initial release.
Custom
March 2012 1.6
  • Added register definitions for address range 0x080–0x085.
Low Latency PHY
March 2012 1.6
  • Removed register definitions for address range 0x080–0x085.
10GBASE-R
February 2012 1.5
  • Added datapath latency numbers for Stratix V devices.
  • Corrected bit range for ERRORED_BLOCK_COUNT.
  • Added statement that the cal_blk_powerdown (0x021) and pma_tx_pll_is_locked (0x022) registers are only available when the Use external PMA control and reconfig option is turned On on the Additional Options tab of the GUI.
  • Clarified that the BER count functionality is for Stratix IV devices only.
  • Removed pma_rx_signaldetect register. The 10GBASE-R PHY does not support this functionality.
XAUI
February 2012 1.5
  • Removed reset bits at register 0x081. The reset implemented Cat register 0x044 provides more comprehensive functionality.
  • Removed pma_rx_signaldetect register. The XAUI PHY does not support this functionality.
PCI Express (PIPE)
February 2012 1.5
  • Updated definition of fixedclk. It can be derived from pll_ref_clk.
Custom
February 2012 1.5
  • Removed register definitions for Low Latency PHY.
Low Latency PHY
February 2012 1.5
  • Added register definitions for Low Latency PHY.
Deterministic Latency PHY
February 2012 1.5
  • Removed pma_rx_signaldetect register. The Deterministic Latency PHY does not support this functionality.
  • Updated the definition of deterministic latency word alignment mode to include the fact that the word alignment pattern, which is currently forced to K28.5 = 0011111010 is always placed in the least significant byte (LSB) of a word with a fixed latency of 3 cycles.
Transceiver Reconfiguration Controller
February 2012 1.5
  • Added DFE.
Introduction
December 2011 1.4
  • Revised discussion of embedded reset controller to include the fact that this reset controller can be disabled for some transceiver PHYs.
10GBASE-R
December 2011 1.4
  • Removed description of calibration block powerdown register (0x021) which is not available for this transceiver PHY.
  • Changed definition of phy_mgmt_clk_reset. This signal is active high and level sensitive.
XAUI
December 2011 1.4
  • Changed definition of phy_mgmt_clk_reset. This signal is active high and level sensitive.
  • Added Arria II GX to device support table.
Interlaken
December 2011 1.4
  • Changed access mode for RX equalization, pre-CDR reverse serial loopback, and post-CDR reverse serial loopback to write only (WO).
  • Removed optional rx_sync_word_err, rx_scrm_err, and rx_framing_err status bits.
  • Changed definition of phy_mgmt_clk_reset. This signal is active high and level sensitive.
PHY IP Core for PCI Express (PIPE)
December 2011 1.4
  • Changed definition of phy_mgmt_clk_reset. This signal is active high and level sensitive.
Custom
December 2011 1.4
  • Added ×N and feedback compensation options for bonded clocks.
  • Added Enable Channel Interface parameter which is required for dynamic reconfiguration of transceivers.
  • Corrected formulas for signal width in top-level signals figure.
  • Changed definition of phy_mgmt_clk_reset. This signal is active high and level sensitive.
Low Latency PHY
December 2011 1.4
  • Added option to disable the embedded reset controller to allow you to create your own reset sequence.
  • Added ×N and feedback compensation options for bonded clocks.
  • Fixed name of phy_mgmt_reset signal. Should be phy_mgmt_clk_reset. Also, a positive edge on this signal initiates a reset.
  • Added Enable Channel Interface parameter which is required for dynamic reconfiguration of transceivers.
  • Corrected formulas for signal width in top-level signals figure.
  • Changed definition of phy_mgmt_clk_reset. This signal is active high and level sensitive.
Deterministic Latency PHY
December 2011 1.4
  • Removed Enable tx_clkout feedback path for TX PLL from the General Options tab of the Deterministic Latency PHY IP Core GUI. This option is unavailable in 11.1 and 11.1 SP1.
  • Changed definition of phy_mgmt_clk_reset. This signal is active high and level sensitive.
Transceiver Reconfiguration Controller
December 2011 1.4
  • Added duty cycle distortion (DCD) signal integrity feature.
  • Added PLL and channel reconfiguration using a memory initialization file (.mif).
  • Added ability to reconfigure PLLs, including the input reference clock or to change the PLL that supplies the high speed serial clock to the serializer without including logic to reconfigure channels.
  • Corrected values for RX equalization gain. 0–4 are available.
  • Corrected logical number in Interface Ordering with Multiple Transceiver PHY Instances.
  • Increased the number of channels that can share a PLL from 5 to 11 when feedback compensation is used.
  • Increased the number of channels that can connect to the Transceiver Reconfiguration Controller from 32 to 64.
  • Added section on requirements for merging PLLs.
Introduction
November 2011 1.3
  • Revised reset section. The 2 options for reset are now the embedded reset controller or user-specified reset controller.
  • Updated directory names in simulation testbench.
10GBASE-R PHY Transceiver
November 2011 1.3
  • Added support for Stratix V devices.
  • Added section discussing transceiver reconfiguration in Stratix V devices.
  • Removed rx_oc_busy signal which is included in the reconfiguration bus.
  • Updated QSF settings to include text strings used to assign values and location of the assignment which is either a pin or PLL.
XAUI Transceiver PHY
November 2011 1.3
  • The pma_tx_pll_is_locked is not available in Stratix V devices.
  • Added base data rate, lane rate, input clock frequency, and PLL type parameters.
  • Updated QSF settings to include text strings used to assign values and location of the assignment which is either a pin or PLL.
  • Added section on dynamic transceiver reconfiguration in Stratix V devices.
  • Removed Timing Constraints section. These constraints are included in the HDL code.
Interlaken Transceiver PHY
November 2011 1.3
  • Added tx_sync_done signal which indicates that all lanes of TX data are synchronized.
  • tx_coreclk_in is required in this release.
  • Added base data rate, lane rate, input clock frequency, and PLL type parameters.
  • Updated QSF settings to include text strings used to assign values and location of the assignment which is either a pin or PLL.
PHY IP Core for PCI Express (PIPE)
November 2011 1.3
  • Added pll_powerdown bit (bit[0] of 0x044) for manual reset control. You must assert this bit for 1 ms for Gen2 operation.
  • Added PLL type and base data rate parameters.
  • Updated QSF settings to include text strings used to assign values and location of the assignment which is either a pin or PLL.
Custom Transceiver PHY
November 2011 1.3
  • Added Arria V and Cyclone V support.
  • Addedbase data rate, lane rate, input clock frequency, and PLL type parameters.
  • Revised reset options. The 2 options for reset are now the embedded reset controller or a user-specified reset logic.
  • Updated QSF settings to include text strings used to assign values and location of the assignment which is either a pin or PLL.
Low Latency PHY
November 2011 1.3
  • Added base data rate, lane rate, input clock frequency, and PLL type parameters.
  • Updated QSF settings to include text strings used to assign values and location of the assignment which is either a pin or PLL.
  • Revised reset options. The 2 options for reset are now the embedded reset controller or a user-specified reset logic.
Deterministic Latency
November 2011 1.3
  • Initial release.
Transceiver Reconfiguration Controller
November 2011 1.3
  • Added MIF support to allow transceiver reconfiguration from a .mif file that may contain updates to multiple settings.
  • Added support for the following features:
  • EyeQ
  • AEQ
  • ATX tuning
  • PLL reconfiguration
  • DC gain and four-stage linear equalization for the RX channels
  • Removed Stratix IV device support.
  • Changed frequency range of phy_mgmt_clk to 100-125 MHz.
All Chapters
July 2011 1.2.1
  • Restricted frequency range of the phy_mgmt_clk to 90–100 MHz for the Transceiver Reconfiguration Controller IP Core chapter. There is no restriction on the frequency of phy_mgmt_clk for Stratix V devices in the 10GBASE-R, XAUI, Interlaken, PHY IP Core for PCI Express, Custom, and Low Latency PHYs; however, to use the same clock source for both, you must restrict this clock to 90–100 MHz.
  • Added column specifying availability of read and write access for PMA analog controls in the Transceiver Reconfiguration Controller IP Core chapter.
  • Renamed Avalon-MM bus in for Transceiver Reconfiguration Controller reconfig_mgmt*.
  • Provided frequency range for phy_mgmt_clk for the XAUI PHY IP Core in Arria II GX, Cyclone IV GX, HardCopy IV, and Stratix IV GX devices.
  • Added register descriptions for the automatic reset controller to the Low Latency PHY IP Core chapter.
  • Added two steps to procedure to reconfigure a PMA control in the Transceiver Reconfiguration Controller chapter.
  • Corrected RX equalization DC gain in Transceiver Reconfiguration Controller chapter. It should be 0–4.
  • Corrected serialization factor column in Low Latency PHY IP Core chapter.
Introduction
May 2011 1.2
  • Added simulation section.
  • Revised Figure 1–1 on page 1–1 to show the Transceiver Reconfiguration Controller as a separately instantiated IP core.
  • Added statement saying that the transceiver PHY IP cores do not support the NativeLink feature of the Quartus II software.
  • Revised reset section.
Getting Started
May 2011 1.2
  • No changes from previous release.
10GBASE-R PHY Transceiver
May 2011 1.2
  • Corrected frequency of pll_ref_clk. Should be 644.53125 MHz, not 644.53725 MHz.
  • Renamed reconfig_fromgxb and reconfig_togxb reconfig_from_xcvr and reconfig_to_xcvr, respectively.
XAUI PHY Transceiver
May 2011 1.2
  • Added support for DDR XAUI
  • Added support for Arria II GZ and HardCopy IV
  • Added example testbench
  • Renamed reconfig_fromgxb and reconfig_togxb reconfig_from_xcvr and reconfig_to_xcvr, respectively.
  • Updated definitions of rx_digital_reset and tx_digital_reset for the soft XAUI implementation in XAUI PHY IP Core Registers.
  • Changed description of rx_syncstatus register and signals to specify 2 bits per channel in hard XAUI and 1 bit per channel in soft XAUI implementations.
  • Corrected bit sequencing for 0x084, 0x085 and 0x088 in XAUI PHY IP Core Registers, as follows:
    • patterndetect = 0x084, bits [15:8]
    • syncstatus = 0x084, bits [7:0]
    • errordetect = 0x085, bits [15:8]
    • disperr = 0x085, bits [7:0]
    • rmfifofull = 0x088, bits [7:4]
    • rmfifoempty = 0x088, bits [3:0]
Interlaken PHY Transceiver
May 2011 1.2
  • Added details about the 0 ready latency for tx_ready.
  • Added PLL support to lane rate parameter description in Interlaken PHY General Options.
  • Moved dynamic reconfiguration for the transceiver outside of the Interlaken PHY IP Core. The reconfiguration signals now connect to a separate Reconfiguration Controller IP Core.
  • Added a reference to PHY IP Design Flow with Interlaken for Stratix V Devices which is a reference design that implements the Interlaken protocol in a Stratix V device.
  • Changed supported metaframe lengths from 1–8191 to 5–8191.
  • Added pll_locked output port.
  • Added indirect_addr register at 0x080 for use in accessing PCS control and status registers.
  • Added new Bonded group size parameter.
PHY IP Core for PCI Express PHY (PIPE)
May 2011 1.2
  • Renamed to PHY IP Core for PCI Express.
  • Moved dynamic reconfiguration for the transceiver outside of the PHY IP Core. The reconfiguration signals now connect to a separate Reconfiguration Controller IP Core.
  • Removed ×2 support.
Custom PHY Transceiver
May 2011 1.2
  • Added presets for the 2.50 GIGE and 1.25GIGE protocols.
  • Moved dynamic reconfiguration for the transceiver outside of the Custom PHY IP Core. The reconfiguration signals now connect to a separate Reconfiguration Controller IP Core.
  • Removed device support for Arria II GX, Arria II GZ, HardCopy IV GX, and Stratix IV GX.
  • Added the following parameters on the General tab:
    • Transceiver protocol
    • Create rx_recovered_clk port
    • Force manual reset control
  • Added optional rx_rmfifoddatainserted, rx_rmfifodatadelted, rx_rlv, and rx_recovered_clk as output signals.
  • Added phy_mgmt_waitrequest to the PHY management interface.
  • Renamed reconfig_fromgxb and reconfig_togxb reconfig_from_xcvr and reconfig_to_xcvr, respectively.
  • Corrected address for 8-Gbps RX PCS status register in Table 9–18 on page 9–20.
  • Added special pad requirement for Byte ordering pattern. Refer to Table 9–6 on page 9–8.
  • Clarified behavior of the word alignment mode. Added note explaining how to disable all word alignment functionality.
Low Latency PHY Transceiver
May 2011 1.2
  • Moved dynamic reconfiguration for the transceiver outside of the Low Latency PHY IP Core. The reconfiguration signals now connect to a separate Reconfiguration Controller IP Core.
  • Moved dynamics reconfiguration for the transceiver outside of the Custom PHY IP Core. The reconfiguration signals now connect to a separate Reconfiguration Controller IP Core.
  • Renamed the tx_parallel_clk signal tx_clkout.
Transceiver Reconfiguration Controller
May 2011 1.2
  • Added Stratix V support. The Transceiver Reconfiguration Controller is only available for Stratix IV devices in the Transceiver Toolkit.
  • Added sections describing the number of reconfiguration interfaces required and restrictions on channel placement.
  • Added pre- and post-serial loopback controls.
  • Changed reconfiguration clock source. In 10.1, the Avalon-MM PHY Management clock was used for reconfiguration. In 11.0, the reconfiguration controller supplies this clock.
Migrating from Stratix IV to Stratix V
May 2011 1.2
  • Added discussion of dynamic reconfiguration for Stratix IV and Stratix V devices.
  • Added information on loopback modes for Stratix IV and Stratix V devices.
  • Added new parameters for Custom PHY IP Core in Stratix V devices.
All Chapters
December 2010 1.11
  • Corrected frequency range for the phy_mgmt_clk for the Custom PHY IP Core in Avalon-MM PHY Management Interface.
  • Added optional reconfig_from_xcvr[67:0] to XAUI Top-Level Signals—Soft PCS and PMA. Provided more detail on size of reconfig_from_xcvr in Dynamic Reconfiguration Interface Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX devices.
  • Removed table providing ordering codes for the Interlaken PHY IP Core. Ordering codes are not required for Stratix V devices using the hard implementation of the Interlaken PHY.
  • Added note to 10GBASE-R release information table stating that “No ordering codes or license files are required for Stratix V devices.”
  • Minor update to the steps to reconfigure a TX or RX PMA setting in the Transceiver Reconfiguration Controller chapter.
Introduction
December 2010 1.1
  • Revised reset diagram.
  • Added block diagram for reset.
  • Removed support for SOPC Builder.
Getting Started
December 2010 1.1
  • Removed description of SOPC Builder design flow. SOPC Builder is not supported in this release.
10GBASE-R PHY Transceiver
December 2010 1.1
    • Added Stratix V support
    • Changed phy_mgmt_address from 16 to 9 bits.
    • Renamed management interface, adding phy_ prefix
    • Renamed block_lock and hi_ber signals rx_block_lock and rx_hi_ber, respectively.
    • Added top-level signals for external PMA and reconfiguration controller in Stratix IV devices. Refer to External PMA and Reconfiguration Signals.
    • Removed the mgmt_burstcount signal.
    • Changed register map to show word addresses instead of a byte offset from a base address.
XAUI PHY Transceiver
December 2010 1.1
  • Added support for Arria II GX and Cyclone IV GX with hard PCS
  • Renamed management interface, adding phy_ prefix
  • Changed phy_mgmt_address from 16 to 9 bits.
  • Renamed many signals. Refer to XAUI Top-Level Signals—Soft PCS and PMA and “XAUI Top-Level Signals–Hard IP PCS and PMA” as appropriate.
  • Changed register map to show word addresses instead of a byte offset from a base address.
  • Removed the rx_ctrldetect and rx_freqlocked signals.
Interlaken PHY Transceiver
December 2010 1.1
  • Added simulation support in ModelSim SE, Synopsys VCS MX, Cadence NCSim
  • Changed number of lanes supported from 4–24 to 1–24.
  • Changed reference clock to be 1/20th rather than 1/10th the lane rate.
  • Renamed management interface, adding phy_ prefix
  • Changed phy_mgmt_address from 16 to 9 bits.
  • Changed many signal names, refer to Top-Level Interlaken PHY Signals.Changed register map to show word addresses instead of a byte offset from a base address.
PCI Express PHY (PIPE)
December 2010 1.1
  • Added simulation support in ModelSim SE
  • Added PIPE low latency configuration option
  • Changed phy_mgmt_address from 16 to 9 bits.
  • Changed register map to show word addresses instead of a byte offset from a base address.
  • Added tx_ready, rx_ready, pipe_txswing, and pipe_rxeleciidle signals
  • Added rx_errdetect, rx_disperr, and rx_a1a2sizeout register fields
Custom PHY Transceiver
December 2010 1.1
  • Added support for 8B/10B encoding and decoding in Stratix V devices
  • Added support for rate matching in Stratix V devices.
  • Added support for Arria II GX, Arria II GZ, HardCopy IV GX, and Stratix IV GX devices
  • Changed phy_mgmt_address from 8 to 9 bits.
  • Added many optional status ports and renamed some signals. Refer to Figure 9–2 on page 9–15 and subsequent signal descriptions.
  • Changed register map to show word addresses instead of a byte offset from a base address.
Low Latency PHY IP Core
December 2010 1.1
  • Renamed management interface, adding phy_ prefix
  • Changed phy_mgmt_address from 16 to 9 bits.
  • Changed register map to show word addresses instead of a byte offset from a base address.
  • Removed rx_offset_cancellation_done signal. Internal reset logic determines when offset cancellation has completed.
  • Removed support for Stratix IV GX devices.
Transceiver Reconfiguration Controller
December 2010 1.1
  • Reconfiguration is now integrated into the XAUI PHY IP Core and 10GBASE-R PHY IP Core.
  • Revised register map to show word addresses instead of a byte offset from a base address.
Migrating from Stratix IV to Stratix V
December 2010 1.1
  • Changed phy_mgmt_address from 16 to 9 bits.
November 2010 1.1
  • Corrected address offsets in PMA Analog Registers. These are byte offsets and should be: 0x00, 0x04, 0x08, 0x0C, 0x10, not 0x00, 0x01, 0x02, 0x03, 0x04.
  • Corrected base address for transceiver reconfiguration control and status registers in PMA Analog Registers. It should be 0x420, not 0x400.
  • Corrected byte offsets in Custom PHY IP Core Registers and PCI Express PHY (PIPE) IP Core Registers. The base address is 0x200. The offsets are 0x000–0x018.
July 2010 1.0
  • Initial release.
Level Two Title