V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

13.4.3.1. Standard PCS Pattern Generators

The Standard PCS includes a pattern generator that generates and verifies the PRBS patterns.

Table 198.   Standard PCS PRBS Patterns

PATTERN

POLYNOMIAL

PRBS-7

X7 + X6 + 1

PRBS-8 X8 + X7 +X3 + X2 + 1

PRBS-10

X10 + X7 + 1

PRBS-15

X15 + X14 + 1

PRBS-23

X23 + X18 + 1

PRBS-31

X31+ X28 + 1

The Standard PCS requires a specific word alignment for the PRBS pattern. You must specify a word alignment pattern in the verifier that matches the generator pattern specified. In the Standard PCS, PRBS patterns available depend upon the PCS-PMA width. The following table below illustrates the patterns are available based upon the PCS-PMA width.

Table 199.  PRBS Patterns in the 8G PCS with PCS-PMA Widths
PCS-PMA Width

8-Bit

10-Bit

16-Bit

20-Bit

PRBS-7

X X X
PRBS-8 X

PRBS-10

X

PRBS 15

X X X X

PRBS 23

X X X

PRBS 31

X X X X

Unlike the 10G PRBS verifier, the Standard PRBS verifier uses the Standard PCS word aligner. You must specify the word aligner size and pattern. The following table lists the encodings for the available choices.

Table 200.  Word Aligner Size and Word Aligner Pattern

PCS-PMA Width

PRBS Patterns

PRBS Pattern Select

Word Aligner Size

Word Aligner Pattern

8-bit

PRBS 7

3’b010

3’b001

0x0000003040

PRBS 8

3’b000

3’b001

0x000000FF5A

PRBS 23

3’b100

3’b001

0x0000003040

PRBS 15

3’b101

3’b001

0x0000007FFF

PRBS 31

3’b110

3’b001

0x000000FFFF

10-bit

PRBS 10

3’b000

3’b010

0x00000003FF

PRBS 15

3’b101

3’b000

0x0000000000

PRBS 31

3’b110

3’b010

0x00000003FF

16-bit

PRBS 7

3’b000

3’b010

0x0000003040

PRBS 23

3’b001

3’b101

0x00007FFFFF

PRBS 15

3’b101

3’b011

0x0000007FFF

PRBS 31

3’b110

3’b011

0x000000FFFF

20-bit

PRBS 7

3’b000

3’b100

0x0000043040

PRBS 23

3’b001

3’b110

0x00007FFFFF

PRBS 15

3’b101

3’b100

0x0000007FFF

PRBS 31

3’b110

3’b110

0x007FFFFFFF

Registers and Values

The following table lists the offsets and registers for the Standard PCS pattern generator and verifier.

Note: All undefined register bits are reserved.
Table 201.  Offsets for the Standard PCS Pattern Generator and Verifier
Offset OffsetBits R/W Name Description
0x97 [9] R/W PRBS TX Enable When set to 1'b1, enables the PRBS generator.
[8:6] R/W PRBS Pattern Select Specifies the encoded PRBS pattern defined in the previous table.
0x99 [9] R/W Clock Power Down TX When set to 1'b1, powers down the PRBS Clock in the transmitter. When set to 1'b0, enables the PRBS generator.
0x141 [0] R/W PRBS TX Inversion Set to 1'b1 to invert the data leaving the PCS block.
0x16D [2] R/W PRBS RX Inversion Set to 1'b1 to invert the data entering the PCS block.
0xA0 [5] R/W PRBS RX Enable When set to 1'b1, enables the PRBS verifier in the receiver.
[4] R/W PRBS Error Clear When set to 1'b1, deasserts rx_prbs_done and restarts the PRBS pattern.
0xA1 [15:14] R/W Sync badcg Must be set to 2'b00 to enable the PRBS verifier.
[13] R/W Enable Comma Detect Must be set to 1'b0 to enable the PRBS verifier.
[11] R/W Enable Polarity Must be set to 1'b0 to enable the PRBS verifier.
[10:8] R/W Word Aligner Size Specifies the word alignment size using the encodings defined in the previous table.
[7:0] R/W Word Aligner Pattern [39:32] Stores the high-order 8 bits of the word aligner pattern as specified in the previous table.
0xA2 [15:0] R/W Word Aligner Pattern [31:16] Stores the middle 16 bits of the word aligner pattern as specified in the previous table.
0xA3 [15:0] R/W Word Aligner Pattern [15:0] Stores the least significant 16 bits from the word aligner pattern as specified in the previous table.
0xA4 [15] R/W Sync State Machine Disable Disables the synchronization state machine. When the PCS-PMA Width is 8 or 10, the value must be 1. When the PCS-PMA Width is 16 or 20, the value must be 0.
0xA6 [5] R/W Auto Byte Align Disable Auto aligns the bytes. Must be set to 1'b0 to enable the PRBS verifier.
0xB8 [13] R/W DW Sync State Machine Enable Enables the double width state machine. Must be set to 1'b0 to enable the PRBS verifier.
0xB9 [11] R/W Deterministic Latency State Machine Enable Enables a deterministic latency state machine. Must be set to 1'b0 to enable the PRBS verifier.
0xBA [11] R/W Clock Power Down RX When set to 1'b0, powers down the PRBS clock in the receiver.