V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

17.2. Transceiver Reconfiguration Controller Performance and Resource Utilization

This section describes the approximate device resource utilization for a the Transceiver Reconfiguration Controller for Stratix V devices. The numbers of combinational ALUTs and logic registers are rounded to the nearest 50.
Note: To close timing, you may need to instantiate multiple instances of the Transceiver Reconfiguration Controller IP Core to the multiple transceiver PHYs in your design to reduce routing delays. However, you cannot connect multiple Transceiver Reconfiguration Controllers to a single transceiver PHY.
Table 319.  Resource Utilization for Stratix V Devices
Component ALUTs Registers Memory Blocks M20Ks Run Time
Transceiver Calibration Functions
Offset Cancellation 500 400 0 0 100 us/channel
Duty cycle calibration 350 400 0 0 70 us/channel
ATX PLL calibration 650 450 0 4 60 us/channel
Analog Features
EyeQ 300 200 0 0 -
AEQ 700 500 0 0 40 us/channel
Reconfiguration Features
Channel and PLL reconfiguration 400 500 0 0 - 17
PLL reconfiguration (only) 250 350 0 0
17 The time to complete these functions depends upon the complexity of the reconfiguration operation.

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