7.18.1. Logical Lane Assignment Restriction
Logical channel 0 should be assigned to either physical transceiver channel 1 or channel 4 of a transceiver bank. However, if you have already created a PCB with a different lane assignment for logical lane 0, you can use the workaround shown in the following example to remove this restriction. This redefines the pma_bonding_master parameter using the Intel® Quartus® Prime Assignment Editor. In this example, the pma_bonding_master was originally assigned to physical channel 1. (The original assignment could also have been to physical channel 4.) The to parameter reassigns the pma_bonding_master to the PHY IP instance name. You must substitute the instance name from your design for the instance name shown in quotation marks
Overriding Logical Channel 0 Channel Assignment Restrictions in Stratix V Devices for ×6 or ×N Bonding
set_parameter -name pma_bonding_master "\"1\"" -to "<PHY IP instance name>"
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