V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public

Visible to Intel only — GUID: nik1398984017594

Ixiasoft

Document Table of Contents

10.4.7. SDC Timing Constraints

The SDC timing constraints and approaches to identify false paths listed for Stratix V Native PHY IP apply to all other transceiver PHYs listed in this user guide. Refer to SDC Timing Constraints of Stratix V Native PHY for details.