V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

17.10. Transceiver Reconfiguration Controller DFE Registers

The DFE is an infinite impulse response filter (non-linear) that compensates for inter-symbol interference (ISI). Because the values of symbols previously detected are known, the DFE engine can estimate the ISI contributed by these symbols and cancel out this ISI by subtracting the predicted value from subsequent symbols.

This mechanism allows DFE to boost the signal to noise ratio of the received data. You can use DFE in conjunction with the receiver's linear equalization and with the transmitter's pre-emphasis feature. DFE is supported by Arria V GZ and Stratix V devices.

DFE automatically runs offset calibration and phase interpolator (PI) phase calibration on all channels after power up. You can run DFE manually to determine the optimal settings by monitoring the BER of the received data at each setting and specify the DFE settings that yield the widest eye.

Note: If you are using the EyeQ monitor with DFE enabled, you must put the EyeQ monitor in 1D mode by writing the EyeQ 1D-eye bit. For more information, refer to EyeQ Offsets and Values.
Note: If you are using a PHY IP that has DFE enabled with a reconfiguration controller and/or if you are using ATX PLLs in your design, then the reference clock to the PHY IP must be stable before the reconfiguration controller is taken out of reset state.

The following table lists the direct DFE registers that you can access using Avalon-MM reads and writes on reconfiguration management interface.

Note: All undefined register bits are reserved.
Table 329.   DFE Registers
Reconfig Addr Bits R/W Register Name Description
7’h18 [9:0] RW logical channel address The logical channel address. Must be specified when performing dynamic updates. The Transceiver Reconfiguration Controller maps the logical address to the physical address.
7’h1A [9] R control and status

Error.When asserted, indicates an invalid channel or address.

[8] R Busy. When asserted, indicates that a reconfiguration operation is in progress.
[1] W Read. Writing a 1 to this bit triggers a read operation.
[0] W Write. Writing a 1 to this bit triggers a write operation.
7’h1B [5:0] RW dfe_offset Specifies the 6-bit offset of the DFE register.
7’h1C [15:0] RW data Reconfiguration data for the transceiver PHY registers.

The following table describes the DFE registers that you can access to change DFE settings.

Note: All undefined register bits are reserved.
Table 330.  DFE Offset and Values
Offset Bits R/W Register Name Description
0x0 [1] RW power on Writing a 0 to this bit powers down DFE in the channel specified.
[0] RW adaptation engine enable Writing a 1 enables the adaptive equalization engine.
0x1 [3:0] RW tap 1 Specifies the coefficient for the first post tap. The valid range is 0–15.
0x2 [3] RW tap 2 polarity

Specifies the polarity of the second post tap as follows:

  • 0: negative polarity
  • 1: positive polarity
[2:0] RW tap 2 Specifies the coefficient for the second post tap. The valid range is 0–7.
0x3 [3] RW tap 3 polarity

Specifies the polarity of the third post tap as follows:

  • 0: negative polarity
  • 1: positive polarity
[2:0] RW tap 3 Specifies the coefficient for the third post tap. The valid range is 0–7.
0x4 [3] RW tap 4 polarity

Specifies the polarity of the fourth post tap as follows:

  • 0: negative polarity
  • 1: positive polarity
[2:0] RW tap 4 Specifies the coefficient for the fourth post tap. The valid range is 0–7.
0x5 [2] RW tap 5 polarity

Specifies the polarity of the fifth post tap as follows:

  • 0: negative polarity
  • 1: positive polarity
[1:0] RW tap 5 Specifies the coefficient for the fifth post tap. The valid range is 0–3.
0xB [0] RW DFE_adaptation Writing a 0 or 1 to this bit turns on the DFE power and initiates triggered DFE mode for the specified channel. Ensure busy bit is 0 to complete the reconfiguration process. Reading (0xB) register bit as 1 and busy bit as 0, indicates that the DFE is in triggered mode. To turn off the triggered DFE mode, write 0 to bit 1 of register 0x0.

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