V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

12.2. Achieving Deterministic Latency

This section provides an overview of the calculation that help you achieve deterministic delay in the Deterministic Latency PHY IP core.

This figure illustrates the TX and RX channels when configured as a wireless basestation communicating to a remote radio head (RRH) using a CPRI or OBSAI interface. The figure also provides an overview of the calculations that guarantee deterministic delay. As this figure illustrates, you can use a general-purpose PLL to generate the clock that drives the TX CMU PLL or an external reference clock input pin.

Figure 60. Achieving Deterministic Latency for the TX and RX DatapathsThe TX and RX Phase Compensation FIFOs always operate in register mode.

To control the total latency through the datapath, use sampling techniques in a delay estimate FIFO to measure the phase difference between the tx_clkout and rx_clkout, and the clock output of the PLL (as shown in above figure) and ensure the delay through the FIFO to a certain accuracy.

Note: Systems that require multiple frequencies in a single transceiver block must use a delay estimate FIFO to determine delay estimates and the required phase adjustments.

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