V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

4.6. 10GBASE-KR Dynamic Reconfiguration from 1G to 10GbE

This topic illustrates the necessary logic to reconfigure between the 1G and 10G data rates.

The following figure illustrates the necessary modules to create a design that can dynamically change between 1G and 10GbE operation on a channel‑by‑channel basis.

In this figure, the colors have the following meanings:

  • Green-Altera- Cores available Intel® Quartus® Prime IP Library, including the 1G/10Gb Ethernet MAC, the Reset Controller, and Transceiver Reconfiguration Controller.
  • Arbitration Logic Requirements Orange-Logic you must design, including the Arbiter and State Machine. Refer to 10GBASE-KR PHY Arbitration Logic Requirements and 10GBASE-KR PHY State Machine Logic Requirements for a description of this logic.
  • White-1G and 10G settings files that you must generate. Refer to Creating a 10GBASE-KR Design for more information.
  • Blue-The 10GBASE-KR PHY IP core available in the Intel® Quartus® Prime IP Library.
Figure 22. Block Diagram for Reconfiguration Example

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