V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

10. Custom PHY IP Core

The Altera Custom PHY IP Core is a generic PHY that you can customize for use in Arria V, Cyclone V, or Stratix V FPGAs. You can connect your application’s MAC-layer logic to the Custom PHY to transmit and receive data at rates of 0.611–6.5536 Gbps for Arria V GX devices, 0.611–6.5536 Gbps in Arria V GT devices, 0.622–9.8304 Gbps in Arria V GZ devices, 0.611–3.125 Gbps for Cyclone V GX devices, 0.611–5.000 Gbps for Cyclone V GT devices, and 0.622–11.0 Gbps for Stratix V devices. You can parameterize the physical coding sublayer (PCS) to include the functions that your application requires.

The following functions are available:

  • 8B/10B encode and decode
  • Three word alignment modes
  • Rate matching
  • Byte ordering

By setting the appropriate options using the MegaWizard Plug-In Manager, you can configure the Custom PHY IP Core to support many standard protocols, including all of the following protocols:

  • Serial Data Converter (SDC(JESD204A))
  • Serial digital interface (SDI)
  • Ethernet (1.25 and 2.50 Gbps)
  • Serial RapidIO ® (SRIO) 1.3
  • Serial ATA (SATA) and serial attached SCSI (SAS) Gen1, Gen2, and Gen3
  • Gigabit‑capable passive optical network (GPON)
Figure 52. Custom PHY IP Core


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