V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

10.4. Interfaces

Figure 53. Custom PHY Top-Level Signals

The variables in Figure 9–2 represent the following parameters:

  • <n>—The number of lanes
  • <w>—The width of the FPGA fabric to transceiver interface per lane
  • <s>— The symbol size
  • <p>—The number of PLLs
Figure 54. Custom PHY Interfaces
Note: By default block diagram shown in the MegaWizard Plug-In Manager labels the external pins with the interface type and places the interface name inside the box. The interface type and name are used in the _hw.tcl file that describes the component. If you turn on Show signals, the block diagram displays all top-level signal names.

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