V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

9.4. PHY for PCIe (PIPE) General Options Parameters

This section describes the PHY IP Core for PCI Express parameters, which you can set using the MegaWizard Plug-In Manager; the settings are available on the General Options tab.
Table 111.  PHY IP Core for PCI Express General Options
Name Value Description
Device family

Stratix V

Arria V GZ

Arria V GX

Arria V GT

Arria V SX

Arria V ST

Supports all Arria V and Stratix V devices.
Number of lanes 1, 2, 4, 8 The total number of duplex lanes.
Protocol version

Gen1 (2.5 Gbps)

Gen2 (5.0 Gbps)

Gen3 (8.0 Gbps)

The Gen1 and Gen2 implement the Intel PHY Interface for PCI Express (PIPE) Architecture PCI Express 2.0 specification. The Gen3 implements the PHY Interface for the PCI Express Architecture PCI Express 3.0 specification.
Gen1 and Gen2 base data rate

1 × Lane rate

2 × Lane rate

4 × Lane rate

8 ×Lane rate

The base data rate is the output clock frequency of the TX PLL. Select a base data rate that minimizes the number of PLLs required to generate all the clocks required for data transmission.
Data rate

2500 Mbps

5000 Mbps

8000 Mbps

Specifies the data rate. This parameter is based on the Protocol version you specify. You cannot change it.
Gen1 and Gen2 PLL type



You can select either the CMU or ATX PLL. The CMU PLL has a larger frequency range than the ATX PLL. The ATX PLL is designed to improve jitter performance and achieves lower channel-to-channel skew; however, it supports a narrower range of data rates and reference clock frequencies. Another advantage of the ATX PLL is that it does not use a transceiver channel, while the CMU PLL does.

Gen3 variants require 2 PLLs for link training which begins in Gen1 and negotiates up to Gen3 if both sides of the link are Gen3 capable.

Gen3 PLL type ATX Gen3 uses the ATX PLL because its jitter characteristics are better than the CMU PLL for data rates above 6 Gbps.
PLL reference clock frequency

100 MHz

125 MHz

You can use either the 100 MHz or 125 MHz input reference clock. (The PCI Express specifications, require an 100 MHz reference clock.)
FPGA transceiver width 8, 16, 32

Specifies the width of the interface between the PHY MAC and PHY (PIPE).The following options are available:

  • Gen1: 8 or 16 bits
  • Gen2: 16 bits
  • Gen3: 32 bits

Using the Gen1 16-bit interface reduces the required clock frequency by half at the expense of extra FPGA resources.

Run length 5–160 Specifies the maximum number of consecutive 0s or 1s that can occur in the data stream. The rx_rlv signal is asserted if the maximum run length is violated.

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