V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

17.30. Merging TX PLLs In Multiple Transceiver PHY Instances

This section describes merging instances of the transceiver PHY.

The Intel® Quartus® Prime Fitter can merge the TX PLLs for multiple transceiver PHY IP cores under the following conditions:

  • The PLLs connect to the same reset pin.
  • The PLLs connect to the same reference clock.
  • The PLLs connect to the same Transceiver Reconfiguration Controller.

The following figure illustrates a design where the CMU PLL in channel 1 provides the clock to three Custom PHY channels and two 10GBASE-R PHY channels.

Figure 101. PLL Shared by Multiple Transceiver PHY IP Cores in a Single Transceiver Bank

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