17.30. Merging TX PLLs In Multiple Transceiver PHY Instances
The Intel® Quartus® Prime Fitter can merge the TX PLLs for multiple transceiver PHY IP cores under the following conditions:
- The PLLs connect to the same reset pin.
- The PLLs connect to the same reference clock.
- The PLLs connect to the same Transceiver Reconfiguration Controller.
The following figure illustrates a design where the CMU PLL in channel 1 provides the clock to three Custom PHY channels and two 10GBASE-R PHY channels.
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