V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

17.5.1. MIF Reconfiguration Management Avalon-MM Master Interface

This section describes the signals that comprise of the MIF Reconfiguration Management Interface. The Transceiver Reconfiguration Controller communicates to an on-chip ROM or any other memory used to store the MIF using this interface.
Table 321.  MIF Reconfiguration Management Avalon-MM Master Interface
Signal Name Direction Description
reconfig_mif_address[31:0] Output This is the Avalon-MM address. This is a byte address.
reconfig_mif_read Output When asserted, signals an Avalon-MM read request.
reconfig_mif_readdata[15:0] Input The read data.
reconfig_mif_waitrequest Input When asserted, indicates that the MIF Avalon-MM slave is not ready to respond to a read request.
cal_busy_in Input

In Arria V and Cyclone V devices, acts as a status port for DCD calibration to prevent simultaneous DCD calibration for multiple channels on the same side of the device. This signal is only available when you select Create optional calibration status ports.

If your design includes more than 1 Transceiver Reconfiguration Controller on the same side of the FPGA, you must daisy chain the tx_cal_busy output ports to the cal_busy_in input ports on the same side of the FPGA. Arria V devices require DCD calibration for channels with data rates equal to or greater than 4.9152 Gbps.

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