V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

12.5.2. Additional Options Parameters for Deterministic Latency PHY

This section describes the settings available on the Additional Options tab for the Deterministic Latency PHY IP core.

Name Value Description
Word alignment mode The word aligner restores word boundaries of received data based on a predefined alignment pattern. The word aligner automatically performs an initial alignment to the specified word pattern after reset deassertion. You can select 1 of the following 2 modes: Deterministic latency state machine or Manual
Word alignment mode Deterministic latency state machine Deterministic latency state machine–In this mode, the RX word aligner automatically searches for the word alignment pattern after reset completes. After the word aligner detects the specified word alignment pattern, it sends RX_CLKSLIP to the RX PMA deserializer indicating the number of bits to slip to compensate for the bits that were slipped to achieve word alignment. When RX_CLKSLIP has a non-zero value, the deserializer either skips one serial bit or pauses the serial clock for one cycle. As a result, the period of the parallel clock could be extended by 1 unit interval (UI) during the clock slip operation. This procedure avoids using the TX bit slipper to ensure constant round-trip delay.
In this mode, the specified word alignment pattern, which is currently forced to K28.5 (0011111010) is always placed in the least significant byte (LSB) of a word with a fixed latency of 3 cycles. User logic can assume the LSB placement. Altera recommends the deterministic latency state machine mode for new designs.
During the word alignment process, the parallel clock shifts the phase to align to the data. This phase shifting will be 2/10 cycles (20%) in 10 bit mode, 2/20 cycles (10%) in 20 bit mode, and 2/40 cycles (5%) in 40 bit mode.

For double-width datapaths using deterministic latency state machine mode, after the initial alignment following the deassertion of reset, the Avalon-MM register big rx_enapatternalign (not available as a signal) must be reasserted to initiate another pattern alignment. Asserting rx_enapatternalign, may cause the extra shifting in the RX datapath if rx_enablepatternalign is asserted while bit slipping is in progress; consequently rx_enapatternalign should only be asserted under the following conditions:

  • rx_syncstatus is asserted
  • rx_bitslipboundaryselectout changes from a non-zero value to zero or 1
Word alignment mode Manual Manual–In this mode, the RX word aligner parses the incoming data stream for a specific alignment character. After it identifies this pattern, it shifts the input stream to align the data and also outputs the number of bits slipped on bitslipboundaryselectout[4:0] for latency compensation on the TX datapath. This mode is provided for backwards compatibility with designs implemented in Stratix IV and Arria II devices.
TX bitslip On/ Off TX bitslip is enabled whenever the word aligner is in Manual alignment mode. The TX bitslipper uses the value of bitslipboundarselect[4:0] to compensate for bits slipped on the RX datapath to achieve deterministic latency.
Enable run length violation checking On/ Off If you turn this option on, you can specify the run length which is the maximum legal number of contiguous 0s or 1s. This option also creates the rx_rlv output signal which is asserted when a run length violation is detected.
Run length 5-160 Specifies the threshold for a run-length violation. Must be a multiple of 5.
Create optional word aligner status ports On/ Off Enable this option to include the rx_patterndetect and rx_syncstatus ports.
Create optional 8B/10B control and status ports On/ Off Enable this option to include the 8B/10B rx_runningdisp, rx_errdetect, and rx_disperr signals at the top level of the Deterministic Latency PHY IP Core.
Create PMA optional status ports On/ Off Enable this option to include the 8B/10B rx_is_lockedtoref, rx_is_lockedtodata, and rx_signaldetect signals at the top level of the Deterministic Latency PHY IP Core.
Avalon data interfaces On/ Off This option is typically required if you are planning to import your Deterministic Latency PHY IP Core into a Qsys system.
Enable embedded reset controller On/ Off When you turn this option On, the embedded reset controller handles reset of the TX and RX channels at power up. If you turn this option Off, you must design a reset controller that manages the following reset signals: tx_digitalreset, tx_analogreset, tx_cal_busy, rx_digitalreset, rx_analogreset, and rx_cal_busy. You may also use the Transceiver PHY Reset Controller to reset the transceivers. For more information, refer to the Transceiver Reconfiguration Controller IP Core.