5.16. 1G/10GbE PHY Register Definitions
You can access the 1G/10GbE registers using the Avalon-MM PHY management interface with word addresses and a 32-bit embedded processor. A single address space provides access to all registers.
- Unless otherwise indicated, the default value of all registers is 0.
- Writing to reserved or undefined register addresses may have undefined side effects.
- To avoid any unspecified bits to be erroneously overwritten, you must perform read-modify-writes to change the register values.
|0xB0||0||RW||Reset SEQ||When set to 1, resets the sequencer. This bit must be used in conjunction with SEQ Force Mode[2:0] . This reset self clears.|
|2||RW||Disable LF Timer||When set to 1, disables the Link Fault timer. When set to 0, the Link Fault timer is enabled.|
|6:4||RW||SEQ Force Mode[2:0]|| Forces the sequencer to a specific protocol. Allows you to change speeds if you have turned on Enable automatic speed detection in the GUI. You must write the Reset SEQ bit to 1 for the Force to take effect. The following encodings are defined:
|0xB1||0||RO||SEQ Link Ready||When asserted, the sequencer is indicating that the link is ready.|
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