V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

17.17. Transceiver Reconfiguration Controller Channel and PLL Reconfiguration

You can use channel and PLL reconfiguration to dynamically reconfigure the channel and PLL settings in a transceiver PHY IP core.

Among the settings that you can change dynamically are the data rate and interface width. Refer to Device Support for Dynamic Reconfiguration for specific information about reconfiguration in Arria V, Cyclone V, and Stratix V devices.

The Transceiver Reconfiguration Controller’s Streamer Module implements channel and PLL reconfiguration. Refer to the Streamer Module Registers for more information about this module.

Note: Channel and PLL reconfiguration are available for the Custom, Low Latency, Deterministic Latency PHY IP Cores, the Arria V Native PHY, the Arria V GZ Native PHY, the Cyclone V Native PHY, and the Stratix V Native PHY.

Did you find the information on this page useful?

Characters remaining:

Feedback Message