V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

5.21. 1G/10GbE Dynamic Reconfiguration from 1G to 10GbE

This topic illustrates the necessary logic to reconfigure between the 1G and 10G data rates.
The following figure illustrates the necessary modules to create a design that can dynamically change between 1G and 10GbE operation on a channel‑by‑channel basis. In this figure, the colors have the following meanings:
  • Green-Altera- Cores available Intel® Quartus® Prime IP Library, including the 1G/10Gb Ethernet MAC, the Reset Controller, and Transceiver Reconfiguration Controller.
  • Orange-Arbitration Logic Requirements Logic you must design, including the Arbiter and State Machine. Refer to1G/10GbE PHY Arbitration Logic Requirements and 1G/10GbE PHY State Machine Logic Requirements for a description of this logic.
  • White-1G and 10G settings files that you must generate. Refer to Creating a 1G/10GbE Design for more information.
  • Blue-The 1G/10GbE PHY IP core available in the Intel® Quartus® Prime IP Library.
Figure 32. Block Diagram for Reconfiguration Example